The following resolution rule is used in logic programming. Derive clause $$\left( {P \vee Q} \right)$$ from clauses $$\left( {P \vee R} \right)$$, $$\left( {Q \vee \neg R} \right)$$.

Which of the following statements related to this rule is FALSE?

$$m$$ identical balls are to be placed in $$n$$ distinct bags. You are given that $$m \ge kn$$, where $$k$$ is a natural number $$ \ge 1$$. In how many ways can the balls be placed in the bags if each bag must contain at least $$k$$ balls?

A processor uses $$2$$-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both $$32$$ bits wide. The memory is byte addressable. For virtual to physical address translation, the $$10$$ most significant bits of the virtual address are used as index into the first level page table while the next $$10$$ bits are used as index into the second level page table. The $$12$$ least significant bits of the virtual address are used as offset within thepage. Assume that the page table entries in both levels of page tables are $$4$$ bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of $$96$$%. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of $$90$$%. Main memory access time is $$10$$ ns, cache access time is $$1$$ ns, and TLB access time is also $$1$$ ns.

Assuming that no page faults occur, the average time taken to access a virtual address is approximately (to the nearest $$0.5$$ ns)

A processor uses $$2$$-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both $$32$$ bits wide. The memory is byte addressable. For virtual to physical address translation, the $$10$$ most significant bits of the virtual address are used as index into the first level page table while the next $$10$$ bits are used as index into the second level page table. The $$12$$ least significant bits of the virtual address are used as offset within thepage. Assume that the page table entries in both levels of page tables are $$4$$ bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of $$96$$%. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of $$90$$%. Main memory access time is $$10$$ ns, cache access time is $$1$$ ns, and TLB access time is also $$1$$ ns.

Suppose a process has only the following pages in its virtual address space: two contiguous code pages starting at virtual address $$0 \times 00000000,$$ two contiguous data pages starting at virtual address $$0 \times 00400000,$$ and a stack page starting at virtual address $$0 \times FFFFF000.$$ The amount of memory required for storing the page tables of this process is