1
GATE CSE 2003
MCQ (Single Correct Answer)
+2
-0.6
A processor uses $$2$$-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both $$32$$ bits wide. The memory is byte addressable. For virtual to physical address translation, the $$10$$ most significant bits of the virtual address are used as index into the first level page table while the next $$10$$ bits are used as index into the second level page table. The $$12$$ least significant bits of the virtual address are used as offset within thepage. Assume that the page table entries in both levels of page tables are $$4$$ bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of $$96$$%. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of $$90$$%. Main memory access time is $$10$$ ns, cache access time is $$1$$ ns, and TLB access time is also $$1$$ ns.

Assuming that no page faults occur, the average time taken to access a virtual address is approximately (to the nearest $$0.5$$ ns)

A
$$1.5$$ ns
B
$$2$$ ns
C
$$3$$ ns
D
$$4$$ ns
2
GATE CSE 2003
MCQ (Single Correct Answer)
+2
-0.6
A processor uses $$2$$-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both $$32$$ bits wide. The memory is byte addressable. For virtual to physical address translation, the $$10$$ most significant bits of the virtual address are used as index into the first level page table while the next $$10$$ bits are used as index into the second level page table. The $$12$$ least significant bits of the virtual address are used as offset within thepage. Assume that the page table entries in both levels of page tables are $$4$$ bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of $$96$$%. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of $$90$$%. Main memory access time is $$10$$ ns, cache access time is $$1$$ ns, and TLB access time is also $$1$$ ns.

Suppose a process has only the following pages in its virtual address space: two contiguous code pages starting at virtual address $$0 \times 00000000,$$ two contiguous data pages starting at virtual address $$0 \times 00400000,$$ and a stack page starting at virtual address $$0 \times FFFFF000.$$ The amount of memory required for storing the page tables of this process is

A
$$8$$ KB
B
$$12$$ KB
C
$$16$$ KB
D
$$20$$ KB
3
GATE CSE 2003
MCQ (Single Correct Answer)
+1
-0.3
Using a larger block size in a fixed block size file system leads to
A
better disk throughput but poorer disk space utilization
B
better disk throughput and better disk space utilization
C
poorer disk throughput but better disk space utilization
D
poorer disk throughput and poorer disk space utilization
4
GATE CSE 2003
MCQ (Single Correct Answer)
+1
-0.3
Which of the following statements is FALSE?
A
In statically typed languages, each variable in a program has a fixed type
B
In un-typed languages, values do not have any types
C
In dynamically typed languages, variables have no types
D
In all statically typed languages, each variable in a program is associated with values of only a single type during the execution of the program
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