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## Marks 1

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A processor X1 operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruc...
GATE CSE 2022
Register renaming is done in pipelined processors
GATE CSE 2012
For a pipelined $$CPU$$ with a single $$ALU$$, consider the following situations $$1.\,\,\,\,\,$$ The $$j+1$$ instructio...
GATE CSE 2003
Comparing the time $$T1$$ taken for a single instruction on a pipelined $$CPU$$ with time $$T2$$ taken on a non-pipeline...
GATE CSE 2000

## Marks 2

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Consider the following instruction sequence where register R1, R2 and R3 are general purpose and MEMORY[X] denotes the c...
GATE CSE 2021 Set 1
A five-stage pipeline has stage delays of 150, 120, 150, 160 and 140 nanoseconds. The registers that are used between th...
GATE CSE 2021 Set 1
Consider a non-pipelined processor operating at 2.5 GHz. It takes 5 clock cycles to complete an instruction. You are goi...
GATE CSE 2020
The instruction pipeline of a $$RISC$$ processor has the following stages: Instruction Fetch $$(IF),$$ Instruction Decod...
GATE CSE 2018
Consider a $$3$$ $$GHz$$ (gigahertz) processor with a three-stage pipeline and stage latencies $${\tau _1},{\tau _2},$$ ...
GATE CSE 2016 Set 2
Suppose the functions $$F$$ and $$G$$ can be computed in $$5$$ and $$3$$ nanoseconds by functional units $${U_F}$$ and \$...
GATE CSE 2016 Set 2
The stage delays in a $$4$$-stage pipeline are $$800, 500, 400$$ and $$300$$ picoseconds. The first stage (with delay $$... GATE CSE 2016 Set 1 Consider the following reservation table for a pipeline having three stages$${S_1},{S_2}$$and$${S_3}.$$The minimum... GATE CSE 2015 Set 3 Consider the sequence of machine instructions given below: .tg {border-collapse:collapse;border-spacing:0;border:none... GATE CSE 2015 Set 2 Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The sa... GATE CSE 2015 Set 1 An instruction pipeline has five stages, namely, instruction fetch$$(IF),$$instruction decode and register fetch$$(ID...
GATE CSE 2014 Set 3
Consider a $$6$$-stage instruction pipeline, where all stages are perfectly balanced. Assume that there is no cycle-time...
GATE CSE 2014 Set 1
Consider the following processors ($$ns$$ stands for nanoseconds). Assume that the pipeline registers have zero latency....
GATE CSE 2014 Set 3
Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction $$(FI),$$ Decode Inst...
GATE CSE 2013
Consider an instruction pipeline with four stages $$\left( {S1,\,S2,\,S3,} \right.$$ and $$\left. {S4} \right)$$ each wi...
GATE CSE 2011
A $$5$$-stage pipelined processor has Instruction Fetch $$(IF),$$ Instruction Decode $$(ID),$$ Operand Fetch $$(OF),$$ P...
GATE CSE 2010
Consider a $$4$$ stage pipeline processor. The number of cycles needed by the four instructions $${\rm I}1,$$ $${\rm I}2... GATE CSE 2009 Which of the following are NOT true in a pipelined processor?$$1.$$Bypassing can handle all RAW hazards$$2.$$Registe... GATE CSE 2008 In an instruction execution pipeline, the earliest that the data$$TLB$$(Translation Look aside Buffer) can be accessed... GATE CSE 2008 The following code is to run on a pipelined processor with one branch delay slot$$\eqalign{ &amp; {{\rm I}_1}:\,\,ADD...
GATE CSE 2008
The use of multiple register windows with overlap causes a reduction in the number of memory accesses for $$1.\,\,\,\,$$...
GATE CSE 2008
Consider a pipelined processor with the following four stages $$\,\,\,\,\,$$$$IF:$$ Instruction Fetch $$\,\,\,\,\,$$$$ID... GATE CSE 2007 A CPU has five stages pipeline and runs at$$1GHz$$frequency. Instruction fetch happens in the first stage of the ... GATE CSE 2006 A$$5$$stage pipelined$$CPU$$has the following sequence of stages$$IF$$-Instruction fetch from instruction memory, ... GATE CSE 2005 A$$4$$-stage pipeline has the stage delays as$$150, 120,160$$and$$140$$nano seconds respectively. Registers that ar... GATE CSE 2004 The performance of a pipelined processor suffers if GATE CSE 2002 ## Marks 5 More An instruction pipeline has five stages where each stage takes$$2$$nanoseconds and all instructions use all five stage... GATE CSE 2000 An instruction pipeline consists of$$4$$stages: Fetch (F), Decode field (D), Execute (E), and Result-Write (W). The$$...
GATE CSE 1999

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