1
GATE EE 2025
MCQ (Single Correct Answer)
+1
-0.33

$$ \text { Assuming ideal op-smps, the circuit represents is } $$

GATE EE 2025 Analog Electronics - Operational Amplifier Question 1 English
A
summing amplifier
B
difference amplifier
C
logarithmic amplifier
D
buffer
2
GATE EE 2025
MCQ (Single Correct Answer)
+2
-0.67
In the circuit, $I_{\mathrm{DC}}$ is an ideal current source. The transistors $M_1$ and $M_2$ are assumed to be biased in saturation, wherein $V_{\text {in }}$ is the input signal and $V_{D C}$ is fixed DC voltage. Both transistors have a small signal resistance of $r_{d s}$ and trans-conductance of $g_m$. The small signal output impedance of this circuit is GATE EE 2025 Analog Electronics - Small Signal Modeling Question 1 English
A
$2 r_{d s}$
B
$\frac{1}{g_m}+r_{d s}$
C
$g_m r_{d s}^2+2 r_{d s}$
D
inifinity
3
GATE EE 2025
MCQ (Single Correct Answer)
+2
-0.67

In the circuit, shown below, if the values of $R$ and $C$ are very large, the form of the output voltage for a very high frequency square wave input, is best represented by

GATE EE 2025 Analog Electronics - Operational Amplifier Question 2 English
A
GATE EE 2025 Analog Electronics - Operational Amplifier Question 2 English Option 1
B
GATE EE 2025 Analog Electronics - Operational Amplifier Question 2 English Option 2
C
GATE EE 2025 Analog Electronics - Operational Amplifier Question 2 English Option 3
D
GATE EE 2025 Analog Electronics - Operational Amplifier Question 2 English Option 4
4
GATE EE 2025
Numerical
+2
-0

The op-amps in the following circuit are ideal. The voltage gain of the circuit is ___________. (Round off to the nearest integer)

GATE EE 2025 Analog Electronics - Operational Amplifier Question 3 English
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