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## Marks 1

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Consider a digital display system (DDS) shown in the figure that displays the contents of register X. A 16-bit code word...
GATE CSE 2022
Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered $$D$$ flip-f...
GATE CSE 2018
We want to design a synchronous counter that counts the sequence $$0-1-0-2-0-3$$ and then repeats. The minimum number of...
GATE CSE 2016 Set 1
The minimum number of $$JK$$ flip-flops required to construct a synchronous counter with the count sequence $$\left( {0,... GATE CSE 2015 Set 2 Consider a 4-bit Johnson counter with an initial value of 0000. The counting sequence of this counter is GATE CSE 2015 Set 1 Let$$k = {2^n}.$$A circuit is built by giving the output of an ݊$$n$$-bit binary counter as input to an$$n$$-to-$${2...
GATE CSE 2014 Set 2
You are given a free running clock with a duty cycle of $$50$$% and a digital waveform $$f$$ which changes only at the n...
GATE CSE 2006
$$SR.$$ latch made by cross coupling two $$NAND$$ gates if $$S=R=0,$$ Then it will result in
GATE CSE 2004

## Marks 2

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Consider a 3-bit counter, designed using T flip-flop, as shown below: Assuming the initial state of the counter gi...
GATE CSE 2021 Set 1
A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flip-flop as follows. The Q output of...
GATE CSE 2015 Set 1
The above synchronous sequential circuit built using $$JK$$ flip-flops is initialized with $${Q_2}{Q_1}{Q_0} = 000.\,\,... GATE CSE 2014 Set 3 Consider the following circuit involving three Dtypes flip-flops used in a certain type of Counter configuration. If a... GATE CSE 2011 Consider the following circuit involving three Dtypes flip-flops used in a certain type of Counter configuration. If a... GATE CSE 2011 Given the following state table of an$$FSM$$with two states$$A$$and$$B,$$one input and one output: If the initial... GATE CSE 2009 The control signal functions of a$$4$$-bit binary counter are given below$$($$where$$X$$“don’t care”$$):$$The coun... GATE CSE 2007 Consider the circuit in the diagram. The$$ \oplus $$operator represents$$EX$$-$$OR.$$The$$D$$flip-flops are initia... GATE CSE 2006 Consider the partial implementation of a$$2$$-bit counter using$$T$$flip-flops following the sequence$$0$$-$$2$$-$$3...
GATE CSE 2004
A 1- input, 2- output synchronous sequential circuit behaves as follows. Let $${z_k},\,{n_k}$$ denote the number of $$0’... GATE CSE 2003 Consider the following circuit with initial state$${Q_0} = {Q_1} = 0.$$The$$D$$Flip-Flops are positive edge triggere... GATE CSE 2001 Consider the circuit given below with initial state$${Q_0} = 1,\,\,{Q_1} = {Q_2} = 0.$$The state of the circuit is giv... GATE CSE 2001 The following arrangement of master-slave flip-flop Has the initial state of$$P, Q$$as$$0, 1$$(respectively). After... GATE CSE 2000 Find the maximum clock frequency at which the counter in Fig., can be operated. Assume that the propagation delay throug... GATE CSE 1991 ## Marks 5 More Consider the synchronous sequential circuit in fig. (a) Draw a state diagram which is implemented by the circuit. Use ... GATE CSE 1996 For the synchronous counter shown in fig. write the truth table of$${Q_0},\,\,{Q_1}$$and$${Q_2} after each pulse st...
GATE CSE 1990

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