The figure shows a digital circuit constructed using negative edge triggered $$J-K$$ flip flops. Assume a starting state of $${Q_2}\,{Q_1}\,{Q_0} = 000.$$ This state $${Q_2}\,{Q_1}\,{Q_0} = 000$$ will repeat after _____ number of cycles of the clock $$CLK.$$

An $$8$$-bit, unipolar Successive Approximation Register type $$ADC$$ is used to convert $$3.5$$ $$V$$ to digital equivalent output. The reference voltage is $$+5 V.$$ The output of the $$ADC,$$ at the end of $$3$$rd clock pulse after the start of conversion, is

In the given circuit, the parameter k is positive, and the power dissipated in the 2 Ω resistor is 12.5 W. The value of k is ________.

For the given circuit the Thevenin equivalent is to be determined. The Thevenin voltage, V_Th (in volt), seen from terminal AB is _________.