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## Marks 1

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The maximum clock frequency in MHz of a 4-stage ripple counter, utilizing flip-flops, with each flip-flop having a propa...
GATE EE 2022
A MOD-2 and a MOD-5 up-counter when cascaded together results in a MOD _________ counter. (in integer).
GATE EE 2022
A cascade of three identical modulo -\$\$5\$\$ counters has an over all modulus of
GATE EE 2014 Set 1
A state diagram of a logic gate which exhibits a delay in the output is shown in the figure, where \$\$X\$\$ is the don't ca...
GATE EE 2014 Set 3
Consider the given circuit. In this circuit, the race around ...
GATE EE 2012
The frequency of the clock signal applied to the rising edge triggered \$\$D\$\$ flip-flop shown in Fig. is \$\$10\$\$ \$\$kHz.\$\$ ...
GATE EE 2002
For a \$\$J\$\$-\$\$K\$\$ flip-flop its \$\$J\$\$ input is tied to its own \$\$Q\$\$ output and its \$\$K\$\$ input is connected to its own ...
GATE EE 1995

## Marks 2

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For the synchronous sequential circuit shown below, the output \$\$Z\$\$ is zero for the initial conditions \$\${Q_A}{Q_B}{Q_C...
GATE EE 2017 Set 2
The current state \$\${Q_A}{Q_B}\$\$ of a two \$\$JK\$\$ flip-flop system is \$\$00.\$\$ Assume that the clock rise-time is much sma...
GATE EE 2016 Set 1
In the following sequential circuit, the initial state (before the first clock pulse) of the circuit is \$\${Q_1}{Q_0}\$\$ \$...
GATE EE 2015 Set 2
The figure shows a digital circuit constructed using negative edge triggered \$\$J-K\$\$ flip flops. Assume a starting state...
GATE EE 2015 Set 1
A \$\$JK\$\$ flip flop can be implemented by \$\$T\$\$ flip flops. Identify the correct implementation.
GATE EE 2014 Set 2
The clock frequency applied to the digital circuit shown in the figure below is \$\$1\$\$ \$\$kHz.\$\$ If the initial state of t...
GATE EE 2013
The state transition diagram for the logic circuit shown is ...
GATE EE 2012
A two-bit counter circuit is shown below It the state \$\${Q_A}{Q_B}\$\$ of the counter at the clock time \$\${t_n}\$\$ is \$\$'...
GATE EE 2011
Select the circuit which will produce the given output \$\$Q\$\$ for the input signals \$\${X_1}\$\$ and \$\${X_2}\$\$ given in the ...
GATE EE 2005
The digital circuit shown in the figure works as a ...
GATE EE 2005
The shift register shown in Fig. is initially loaded with the bit pattern \$\$1010.\$\$ Subsequently the shift register is c...
GATE EE 2003
The counter shown in Fig. is initially in state \$\${Q_2} = 0,\,{Q_1} = 1,\,{Q_0} = 0.\$\$ With reference to the \$\$CLK\$\$ inp...
GATE EE 2000
A dual-slope analog-to-digital converter uses an \$\$N\$\$-bit counter. When the input signal \$\${V_a}\$\$ is being integrated,...
GATE EE 2000

## Marks 5

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The digital circuit shown in figure generates a modified clock pulse at the output. Choose the correct output waveform f...
GATE EE 2004
The ripple counter shown in Fig. is made up negative edge triggered \$\$J\$\$-\$\$E\$\$ flips flops. The signal levels at \$\$J\$\$ ...
GATE EE 2002
For the ring counter shown in Fig. find the steady state sequence if the initial state of the counters is \$\$1110\,\,(i.e...
GATE EE 2001
\$\$(a)\$\$ Construct the truth table for the circuit given in Figure \$\${Q_1},{Q_2}\$\$ and \$\${Q_3}\$\$ are outputs and the cloc...
GATE EE 1998

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