1
GATE CSE 2016 Set 1
Numerical
+1
-0
A processor can support a maximum memory of $$4$$ $$GB,$$ where the memory is word-addressable (a word consists of two bytes). The size of the address bus of the processor is at least ___________ bits.
2
GATE CSE 2016 Set 1
Numerical
+2
-0
The size of the data count register of a $$DMA$$ controller is $$16$$ bits. The processor needs to transfer a file of $$29,154$$ kilobytes from disk to main memory. The memory is byte addressable. The minimum number of times the $$DMA$$ controller needs to get the control of the system bus from the processor to transfer the file from the disk to main memory is ___________.
3
GATE CSE 2016 Set 1
Numerical
+2
-0
The stage delays in a $$4$$-stage pipeline are $$800, 500, 400$$ and $$300$$ picoseconds. The first stage (with delay $$800$$ picoseconds) is replaced with a functionally equivalent design involving two stages with respective delays $$600$$ and $$350$$ picoseconds. The throughput increase of the pipeline is percent.
4
GATE CSE 2016 Set 1
+1
-0.3
A queue is implemented using an array such that ENQUEUE and DEQUEUE operations are performed efficiently. Which one of the following statements is CORRECT ($$n$$ refers to the number of items in the queue)?
A
Both operations can be performed in $$O\left( 1 \right)$$ time
B
At most one operation can be performed in $$O\left( 1 \right)$$ time but the worst case time for the other operation will be $$\Omega \left( n \right)$$
C
The worst case time complexity for both operations will be $$\Omega \left( n \right)$$
D
Worst case time complexity for both operations will be $$\Omega \left( {\log n} \right)$$
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