1
GATE CSE 2016 Set 1
MCQ (Single Correct Answer)
+2
-0.6
Consider that B wants to send a message m that is digitally signed to A. Let the pair of private and public keys for A and B be denoted by $$K_x^ - $$ and $$K_x^ + $$ for x = A, B, respectively. Let Kx(m) represent the operation of encrypting m with a key Kx and H(m) represent the message digest. Which one of the following indicates the CORRECT way of sending the message m along with the digital signature to A?
A
$$\left\{ {m,K_B^ + \left( {H\left( m \right)} \right)} \right\}$$
B
$$\left\{ {m,K_B^ - \left( {H\left( m \right)} \right)} \right\}$$
C
$$\left\{ {m,K_A^ - \left( {H\left( m \right)} \right)} \right\}$$
D
$$\left\{ {m,K_A^ + (m)} \right\}$$
2
GATE CSE 2016 Set 1
Numerical
+1
-0
A processor can support a maximum memory of $$4$$ $$GB,$$ where the memory is word-addressable (a word consists of two bytes). The size of the address bus of the processor is at least ___________ bits.
Your input ____
3
GATE CSE 2016 Set 1
Numerical
+2
-0
The size of the data count register of a $$DMA$$ controller is $$16$$ bits. The processor needs to transfer a file of $$29,154$$ kilobytes from disk to main memory. The memory is byte addressable. The minimum number of times the $$DMA$$ controller needs to get the control of the system bus from the processor to transfer the file from the disk to main memory is ___________.
Your input ____
4
GATE CSE 2016 Set 1
Numerical
+2
-0
The stage delays in a $$4$$-stage pipeline are $$800, 500, 400$$ and $$300$$ picoseconds. The first stage (with delay $$800$$ picoseconds) is replaced with a functionally equivalent design involving two stages with respective delays $$600$$ and $$350$$ picoseconds. The throughput increase of the pipeline is percent.
Your input ____
EXAM MAP
Medical
NEETAIIMS
Graduate Aptitude Test in Engineering
GATE CSEGATE ECEGATE EEGATE MEGATE CEGATE PIGATE IN
Civil Services
UPSC Civil Service
Defence
NDA
Staff Selection Commission
SSC CGL Tier I
CBSE
Class 12