1
GATE CSE 2023
Numerical
+1
-0

A keyboard connected to a computer is used at a rate of 1 keystroke per second. The computer system polls the keyboard every 10 ms (milli seconds) to check for a keystroke and consumes 100 $$\mu$$s (micro seconds) for each poll. If it is determined after polling that a key has been pressed, the system consumes an additional 200 $$\mu$$s to process the keystroke. Let $$T_1$$ denote the fraction of a second spent in polling and processing a keystroke.

In an alternative implementation, the system uses interrupts instead of polling. An interrupt is raised for every keystroke. It takes a total of 1 ms for servicing an interrupt and processing a keystroke. Let $$T_2$$ denote the fraction of a second spent in servicing the interrupt and processing a keystroke.

The ratio $${{{T_1}} \over {{T_2}}}$$ is __________. (Rounded off to one decimal place)

Your input ____
2
GATE CSE 2023
MCQ (Single Correct Answer)
+2
-0.67

Consider the given C-code and its corresponding assembly code, with a few operands U1-U4 being unknown. Some useful information as well as the semantics of each unique assembly instruction is annotated as inline comments in the code. The memory is byte-addressable.

GATE CSE 2023 Computer Organization - Machine Instructions and Addressing Modes Question 5 English

Which one of the following options is a CORRECT replacement for operands in the position (U1, U2, U3, U4) in the above assembly code?

A
(8, 4, 1, L02)
B
(3, 4, 4, L01)
C
(8, 1, 1, L02)
D
(3, 1, 1, L01)
3
GATE CSE 2023
MCQ (Single Correct Answer)
+2
-0.67

A 4 kilobyte (KB) byte-addressable memory is realized using four 1 KB memory blocks. Two input address lines (IA4 and IA3) are connected to the chip select (CS) port of these memory blocks through a decoder as shown in the figure. The remaining ten input address lines from IA11-IA0 are connected to the address port of these blocks. The chip select (CS) is active high.

GATE CSE 2023 Computer Organization - Memory Interfacing Question 9 English

The input memory address (IA11-IA0), in decimal, for the starting locations (Addr=0) of each block (indicated as X1, X2, X3, X4 in the figure) are among the options given below. Which one of the following options is CORRECT?

A
(0, 1, 2, 3)
B
(0, 1024, 2048, 3072)
C
(0, 8, 16, 24)
D
(0, 0, 0, 0)
4
GATE CSE 2023
Numerical
+2
-0

An 8-way set associative cache of size 64 KB (1 KB = 1024 bytes) is used in a system with 32-bit address. The address is sub-divided into TAG, INDEX, and BLOCK OFFSET.

The number of bits in the TAG is __________.

Your input ____
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