1
GATE CSE 2019
MCQ (Single Correct Answer)
+2
-0.67

Consider three machines M, N, and P with IP addresses 100.10.5.2, 100.10.5.5, and 100.10.5.6 respectively. The subnet mask is set to 255.255 .255 .252 for all the three machines. Which one of the following is true?

A
$\mathrm{M}, \mathrm{N}$, and P all belong to the same subnet
B
Only M and N belong to the same subnet
C
Only N and P belong to the same subnet
D
M, N, and P belong to three different subnets
2
GATE CSE 2019
MCQ (Single Correct Answer)
+2
-0.67

Suppose that in an IP-over-Ethernet network, a machine X wishes to find the MAC address of another machine Y in its subnet. Which one of the following techniques can be used for this?

A
X sends an ARP request packet to the local gateway's IP address which then finds the MAC address of Y and sends to X
B
X sends an ARP request packet to the local gateway's MAC address which then finds the MAC address of Y and sends to X
C
X sends an ARP request packet with broadcast MAC address in its local subnet
D
X sends an ARP request packet with broadcast IP address in its local subnet
3
GATE CSE 2019
MCQ (Single Correct Answer)
+1
-0.33
The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has 16 address lines denoted by A15 to A0. What is the range of addresses (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal? GATE CSE 2019 Computer Organization - Memory Interfacing Question 14 English
A
C800 to CFFF
B
C800 to C8FF
C
DA00 to DFFF
D
CA00 to CAFF
4
GATE CSE 2019
MCQ (Single Correct Answer)
+1
-0.33
A certain processor uses a fully associative cache of size 16 kB. The cache block size is 16 bytes. Assume that the main memory is byte addressable and uses a 32-bit address. How many bits are required for the Tag and the Index fields resectively in the addresses generated by the processor?
A
28 bits and 4 bits
B
24 bits and 4 bits
C
24 bits and 0 bits
D
28 bits and 0 bits
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