1
GATE CSE 2011
MCQ (Single Correct Answer)
+2
-0.6
Consider a network with five nodes, N1 to N5, as shown below. GATE CSE 2011 Computer Networks - Routing Algorithm Question 5 English

The network uses a Distance Vector Routing protocol. Once the routes have stabilized, the distance vectors at different nodes are as following

N1 : ( 0, 1, 7, 8, 4 )
N2 : ( 1, 0, 6, 7, 3 )
N3 : ( 7, 6, 0, 2, 6 )
N4 : ( 8, 7, 2, 0, 4 )
N5 : ( 4, 3, 6, 4, 0 )

Each distance vector is the distance of the best known path at that instance to nodes, N1 to N5, where the distance to itself is 0. Also, all links are symmetric and the cost is identical in both directions. In each round, all nodes exchange their distance vectors with their respective neighbors. Then all nodes update their distance vectors. In between two rounds, any change in cost of a link will cause the two incident nodes to change only that entry in their distance vectors

The cost of link N2 - N3 reduces to 2 in (both directions). After the next round of updates, what will be the new distance vector at node, N3?

A
(3, 2, 0, 2, 5)
B
(3, 2, 0, 2, 6)
C
(7, 2, 0, 2, 5)
D
(7, 2, 0, 2, 6)
2
GATE CSE 2011
MCQ (Single Correct Answer)
+1
-0.3
Consider different activities related to email:

m1: Send an email from a mail client to a mail server
m2: Download an email from mailbox server to a mail client
m3: Checking email in a web browser

Which is the application level protocol used in each activity?
A
m1: HTTP m2: SMTP m3: POP
B
m1: SMTP m2: FTP m3: HTTP
C
m1: SMTP m2: POP m3: HTTP
D
m1: POP m2: SMTP m3: IMAP
3
GATE CSE 2011
MCQ (Single Correct Answer)
+1
-0.3
A layer-4 firewall (a device that can look at all protocol headers up to the transport layer) CANNOT
A
block entire HTTP traffic during 9:00 PM and 5:00 AM
B
block all ICMP traffic
C
stop incoming traffic from a specific IP address but allow outgoing traffic to the same IP address
D
block TCP traffic from a specific user on a multi-user system during 9:00 PM and 5:00 AM
4
GATE CSE 2011
MCQ (Single Correct Answer)
+2
-0.6
An $$8KB$$ direct-mapped write-back cache is organized as multiple blocks, each of size $$32$$-bytes. The processor generates $$32$$-bit addresses. The cache controller maintains the tag information for each cache block comprising of the following.
$$\,\,\,\,$$$$1$$ Valid bit
$$\,\,\,\,$$$$1$$ Modified bit

As many bits as the minimum needed to identify the memory block mapped in the cache.

What is the total size of memory needed at the cache controller to store meta-data (tags) for the cache?

A
$$4864$$ bits
B
$$6144$$ bits
C
$$6656$$ bits
D
$$5376$$ bits
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