1
GATE CSE 1996
+2
-0.6
Consider the circuit in Fig. Which has a four bit binary number $${b_3}\,{b_2}\,{b_1}\,{b_0}\,$$ as input and a five bit binary number $${d_3}\,{d_2}\,{d_1}\,{d_0}\,$$ as output. The circuit implements:
A
Binary to Hex conversion
B
Binary to $$BCD$$ conversion
C
Binary to grey code conversion
D
Binary to radix -$$12$$ conversion
2
GATE CSE 1996
+2
-0.6
Consider the circuit in fig shown $$f$$ implements
A
$$\overline A \overline B C + \overline A B\overline C + ABC$$
B
$$A+B+C$$
C
$$A \oplus B \oplus C$$
D
$$AB + BC + CA$$
3
GATE CSE 1996
Subjective
+5
-0
Consider the synchronous sequential circuit in fig.

(a) Draw a state diagram which is implemented by the circuit. Use the following names for the states corresponding to the values of flip-flops as given below.

(b) Given that the initial state of the circuit is $${S_4},$$ identify the set of states which are not reachable.

4
GATE CSE 1996
+2
-0.6
Which one of the following is false? Read $$\wedge$$ as AND, $$\vee$$ as OR, $$\sim$$ as NOT, $$\to$$ as one way implication and $$\leftrightarrow$$ two way implication.
A
$$\left( {\left( {x \to y} \right) \wedge x} \right) \to y$$
B
$$\left( {\left( { \sim x \to y} \right) \wedge \left( { \sim x \to \sim y} \right)} \right) \to x$$
C
$$\left( {x \to \left( {x \vee y} \right)} \right)$$
D
$$\left( {\left( {x \vee y} \right) \leftrightarrow \left( { \sim x \to \sim y} \right)} \right)$$
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