In the given figure, plant $G_p(s)=\frac{2.2}{(1+0.1 s)(1+0.4 s)(1+1.2 s)}$ and compensator $G_c(s)=K\left[\frac{1+T_1 s}{1+T_2 s}\right]$.

The external disturbance input is $D(s)$. It is desired that when the disturbance is a unit step, the steady state error should not exceed 0.1 unit. The minimum value of $K$ is ____________. . (Round off to 2 decimal places)

$$ \text { The state space representation of a first-order system is given as } $$

$$ \begin{aligned} & \dot{x}=-x+u \\ & y=x \end{aligned} $$

Where, $x$ is the state variable, $u$ is the control input and $y$ is the controlled output. Let $u=-k x$ be the control law, where $K$ is the controller gain. To place a closed loop pole at -2 , the value of $k$ is $\_\_\_\_$

A 16 -bit synchronous binary up-counter is clocked with a frequency $f_{c l k}$. The two most significant bits are ORed together to form an output $Y$. Measurements shows that $Y$ is periodic and the duration for which $Y$ the remains high in each period is 24 ms . The clock frequency $f_{\text {clk }}$ is $\_\_\_\_$ MHz. (Round off to 2 decimal places)

A counter is constructed with three D flip-flops. The input-output pairs are named as $\left(D_0, Q_0\right)$, $\left(D_1, Q_1\right)$ and $\left(D_2, Q_2\right)$, where the subscript 0 denotes LSB. The output sequence is desired to be Graycode sequence $000,001,011,010,110,111,101$ and 100 , repeating periodically. Note that the bits are listed in the $Q_2 Q_1 Q_0$ format. The combination logic expression for $D_1$ is