Two hosts are connected via a packet switch with $${10^7}$$ bits per second links. Each link has a propagation delay of $$20$$ micro-seconds. The switch begins forwarding a packet $$35$$ microseconds after it receives the same. If $$10000$$ bits of data are to be transmitted between the two hosts using a packet size of $$5000$$ bits, the time elapsed between the transmission of the first bit of data and the reception of the last bit of the data in microseconds is____________.

Consider a machine with a byte addressable main memory of $${2^{20}}$$ bytes, block size of $$16$$ bytes and a direct mapped cache having $${2^{12}}$$ cache lines. Let the addresses of two consecutive bytes in main memory be $${\left( {E201F} \right)_{16}}$$ and $${\left( {E2020} \right)_{16}}$$. What are the tag and cache line address (in $$hex$$) for main memory address $${\left( {E201F} \right)_{16}}$$?

Consider the following code sequence having five instructions $${I_1}$$ to $${I_5}$$. Each of these instructions has the following format.

$$\,\,\,\,\,\,\,\,\,\,\,\,\,\,OP\,\,Ri,\,\,Rj,\,\,Rk$$

where operation $$OP$$ is performed on contents of registers $$Rj$$ and $$Rk$$ and the result is stored in register $$Ri.$$

$$\eqalign{ & \,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,{I_1}:ADD\,\,\,R1,\,R2,\,R3 \cr & \,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,{I_2}:MUL\,\,R7,\,R1,\,R3 \cr & \,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,{I_3}:SUB\,\,\,\,R4,\,R1,\,R5 \cr & \,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,{I_4}:ADD\,\,\,R3,\,R2,\,R4 \cr & \,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,{I_5}:MUL\,\,\,R7,\,R8,\,R9 \cr} $$

Consider the following three statements.

$$\,\,\,\,\,\,S1:\,\,$$ There is an anti-dependence between instructions $${L_2}$$ and $${L_5}$$
$$\,\,\,\,\,\,S2:\,\,$$ There is an anti-dependence between instructions $${L_2}$$ and $${L_4}$$
$$\,\,\,\,\,\,S3:\,\,$$ Within an instruction pipeline an anti-dependence always creates one or more stalls

Which one of above statements is/are correct?

Consider the following reservation table for a pipeline having three stages $${S_1},{S_2}$$ and $${S_3}.$$

The minimum average latency $$(MAL)$$ is ________.