The minimum average latency $$(MAL)$$ is ________.
$$\,\,\,\,\,\,\,\,\,\,\,\,\,\,OP\,\,Ri,\,\,Rj,\,\,Rk$$
where operation $$OP$$ is performed on contents of registers $$Rj$$ and $$Rk$$ and the result is stored in register $$Ri.$$
$$\eqalign{ & \,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,{I_1}:ADD\,\,\,R1,\,R2,\,R3 \cr & \,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,{I_2}:MUL\,\,R7,\,R1,\,R3 \cr & \,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,{I_3}:SUB\,\,\,\,R4,\,R1,\,R5 \cr & \,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,{I_4}:ADD\,\,\,R3,\,R2,\,R4 \cr & \,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,{I_5}:MUL\,\,\,R7,\,R8,\,R9 \cr} $$
Consider the following three statements.
$$\,\,\,\,\,\,S1:\,\,$$ There is an anti-dependence between instructions $${L_2}$$ and $${L_5}$$
$$\,\,\,\,\,\,S2:\,\,$$ There is an anti-dependence between instructions $${L_2}$$ and $${L_4}$$
$$\,\,\,\,\,\,S3:\,\,$$ Within an instruction pipeline an anti-dependence always creates one or more stalls
Which one of above statements is/are correct?