1
GATE CSE 2010
MCQ (Single Correct Answer)
+2
-0.6
A computer system has an $$L1$$ cache, an $$L2$$ cache, and a main memory unit connected as shown below. The block size in $$L1$$ cache is $$4$$ words. The block size in $$L2$$ cache is $$16$$ words. The memory access times are $$2$$ nanoseconds, $$20$$ nanoseconds and $$200$$ nanoseconds for $$L1$$ cache, $$L2$$ cache and main memory unit respectively. GATE CSE 2010 Computer Organization - Memory Interfacing Question 21 English

When there is a miss in both $$L1$$ cache and $$L2$$ cache, first a block is transferred from main memory to $$L2$$ cache, and then a block is transferred from $$L2$$ cache to $$L1$$ cache.
What is the total time taken for these transfers?

A
$$222$$ nanoseconds
B
$$888$$ nanoseconds
C
$$902$$ nanoseconds
D
$$968$$ nanoseconds
2
GATE CSE 2010
MCQ (Single Correct Answer)
+2
-0.6
A computer system has an $$L1$$ cache, an $$L2$$ cache, and a main memory unit connected as shown below. The block size in $$L1$$ cache is $$4$$ words. The block size in $$L2$$ cache is $$16$$ words. The memory access times are $$2$$ nanoseconds, $$20$$ nanoseconds and $$200$$ nanoseconds for $$L1$$ cache, $$L2$$ cache and main memory unit respectively. GATE CSE 2010 Computer Organization - Memory Interfacing Question 22 English

When there is a miss in $$L1$$ cache and a hit in $$L2$$ cache, a block is transferred from $$L2$$ cache to $$L1$$ cache. What is the time taken for this transfer?

A
$$2$$ nanoseconds
B
$$20$$ nanoseconds
C
$$22$$ nanoseconds
D
$$88$$ nanoseconds
3
GATE CSE 2010
MCQ (Single Correct Answer)
+2
-0.6
A $$5$$-stage pipelined processor has Instruction Fetch $$(IF),$$ Instruction Decode $$(ID),$$ Operand Fetch $$(OF),$$ Perform Operation $$(PO)$$ and Write Operand $$(WO)$$ stages. The $$IF, ID, OF$$ and $$WO$$ stages take $$1$$ clock cycle each for any instruction. The $$PO$$ stage takes $$1$$ clock cycle for $$ADD$$ and $$SUB$$ instructions, $$3$$ clock cycles for $$MUL$$ instruction, and $$6$$ clock cycles for $$DIV$$ instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions? GATE CSE 2010 Computer Organization - Pipelining Question 25 English
A
$$13$$
B
$$15$$
C
$$17$$
D
$$19$$
4
GATE CSE 2010
MCQ (Single Correct Answer)
+2
-0.6
A hash table of length 10 uses open addressing with hash function h(k)=k mod 10, and linear probing. After inserting 6 values into an empty hash table, the table is as shown below GATE CSE 2010 Data Structures - Hashing Question 9 English How many different insertion sequences of the key values using the same hash function and linear probing will result in the hash table shown above?
A
10
B
20
C
30
D
40
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