Consider a system with a processor and a 4 KB direct mapped cache with block size of 16 bytes. The system has a 16 MB physical memory. Four words $\mathrm{P}, \mathrm{Q}, \mathrm{R}$, and S are accessed by the processor in the same order 10 times. That is, there are a total of 40 memory references in the sequence $\mathrm{P}, \mathrm{Q}, \mathrm{R}, \mathrm{S}, \mathrm{P}, \mathrm{Q}, \mathrm{R}, \mathrm{S}, \ldots$

Assume that the cache memory is initially empty. The physical addresses of the words are given below (1 word $=1$ byte).

P: 0x845B32, Q: 0x845B26, R: 0x845B36, S: 0x846B32

Which of the following statements is/are true?

Note: $1 \mathrm{~K}=2^{10}$ and $1 \mathrm{M}=2^{20}$

Consider a system with 1 MB physical memory and a word length of 1 byte. The system uses a direct mapped cache, with block numbers starting from 0 . The word with physical address 0xA2C28 is mapped to the cache block number $176_{10}$. The maximum possible size of the cache (in KB ) for this configuration is $\_\_\_\_$ . (answer in integer)

Note: $1 \mathrm{~K}=2^{10}$ and $1 \mathrm{M}=2^{20}$

A non-pipelined instruction execution unit that operates at 1.6 GHz clock takes an average of 5 clock cycles to complete the execution of an instruction. To improve the performance, the system was pipelined with a goal of achieving an average throughput of one instruction per clock cycle. However, it could operate only at 1.2 GHz due to pipeline overheads. While executing a program in the pipelined design, $30 \%$ of instructions encountered a stall of 2 cycles due to pipeline hazards. The speed-up obtained by the pipelined design over the non-pipelined one for this program is $\_\_\_\_$ (rounded off to two decimal places)

Note: $1 \mathrm{G}=10^9$

The set T represents various traversals over binary tree. The set S represents the order of visiting nodes during a traversal.

$$ \begin{array}{ll}\,\,\,\,\, \text {  T } &\,\,\,\,\,\, \text { S } \\ \text { I: } \text { Inorder } & \text { L: left subtree, node, right subtree } \\ \text { II: } \text { Preorder } & \text { M: node, left subtree, right subtree } \\ \text { III: } \text { Postorder } & \text { N: left subtree, right subtree, node } \end{array} $$

Which one of the following is the correct match from $T$ to $S$ ?