1
GATE CSE 2026 Set 2
MCQ (Single Correct Answer)
+1
-0

Consider the following two statements about interrupt handling mechanisms in a CPU.

S1: In non-vectored interrupt mechanism, it usually takes more time to start the Interrupt Service Routine (ISR) when compared to that in a vectored interrupt mechanism.

S2: In daisy-chain interrupt mechanism, the CPU polls all the input devices individually to determine the source of the interrupt.

Which one of the following options is correct with respect to S1 and S2?

A

Both S 1 and S 2 are true

B

Both S 1 and S 2 are false

C

S1 is true and S2 is false

D

S1 is false and S2 is true

2
GATE CSE 2026 Set 2
MCQ (Single Correct Answer)
+2
-0

Consider a processor that has 16 general purpose registers and it uses 2-byte instruction format for all its instructions. Variable-sized opcodes are permitted. There are three different types of instructions; M-type, R-type, and C-type. Each M-type instruction has 2 register operands and a 6 -bit immediate operand. Each R-type instruction has 3 register operands. Each C-type instruction has a register operand and a 6-bit offset value. If there are 2 unique M-type opcodes and 7 unique R-type opcodes, which one of the following options gives the maximum number of unique opcodes possible for C-type instructions?

A

8

B

4

C

64

D

16

3
GATE CSE 2026 Set 2
MCQ (More than One Correct Answer)
+2
-0

Consider a system with a processor and a 4 KB direct mapped cache with block size of 16 bytes. The system has a 16 MB physical memory. Four words $\mathrm{P}, \mathrm{Q}, \mathrm{R}$, and S are accessed by the processor in the same order 10 times. That is, there are a total of 40 memory references in the sequence $\mathrm{P}, \mathrm{Q}, \mathrm{R}, \mathrm{S}, \mathrm{P}, \mathrm{Q}, \mathrm{R}, \mathrm{S}, \ldots$

Assume that the cache memory is initially empty. The physical addresses of the words are given below (1 word $=1$ byte).

P: 0x845B32, Q: 0x845B26, R: 0x845B36, S: 0x846B32

Which of the following statements is/are true?

Note: $1 \mathrm{~K}=2^{10}$ and $1 \mathrm{M}=2^{20}$

A

Every access to P results in a cache miss

B

Every access to R results in a cache hit

C

Every access to $Q$ results in a cache miss

D

Except the first access to S , all subsequent accesses to S result in cache hits

4
GATE CSE 2026 Set 2
Numerical
+2
-0

Consider a system with 1 MB physical memory and a word length of 1 byte. The system uses a direct mapped cache, with block numbers starting from 0 . The word with physical address 0xA2C28 is mapped to the cache block number $176_{10}$. The maximum possible size of the cache (in KB ) for this configuration is $\_\_\_\_$ . (answer in integer)

Note: $1 \mathrm{~K}=2^{10}$ and $1 \mathrm{M}=2^{20}$

Your input ____