1
GATE CSE 2026 Set 2
Numerical
+2
-0

Consider a new TCP connection between a sender and a receiver. The receiver advertised window is constant at 48 KB , the maximum segment size (MSS) is 2 KB , and the slow start threshold for TCP congestion control is 16 KB . Assume that there are no timeouts or duplicate acknowledgements. The number of rounds of transmission required for the congestion control algorithm of the TCP connection to reach the congestion avoidance phase is $\_\_\_\_$ . (answer in integer)

Note: $1 \mathrm{~K}=2^{10}$

Your input ____
2
GATE CSE 2026 Set 2
Numerical
+2
-0

It is necessary to design a link-layer protocol between two hosts that are directly connected over a lossless link of length 3000 kilometers. Assume that the link bandwidth is $10^8$ bits per second and that the propagation delay in the link is 5 nanoseconds per meter. Every transmitted data byte is assigned a unique sequence number.

Let $N$ be the minimum number of bits needed for the sequence number field in the protocol header such that

(i) the sequence numbers do not wrap around before 60 seconds, and

(ii) the maximum utilization of the link is achieved.

The value of $N$ is $\_\_\_\_$ . (answer in integer)

Your input ____
3
GATE CSE 2026 Set 2
MCQ (Single Correct Answer)
+1
-0

Consider the following two statements about interrupt handling mechanisms in a CPU.

S1: In non-vectored interrupt mechanism, it usually takes more time to start the Interrupt Service Routine (ISR) when compared to that in a vectored interrupt mechanism.

S2: In daisy-chain interrupt mechanism, the CPU polls all the input devices individually to determine the source of the interrupt.

Which one of the following options is correct with respect to S1 and S2?

A

Both S 1 and S 2 are true

B

Both S 1 and S 2 are false

C

S1 is true and S2 is false

D

S1 is false and S2 is true

4
GATE CSE 2026 Set 2
MCQ (Single Correct Answer)
+2
-0

Consider a processor that has 16 general purpose registers and it uses 2-byte instruction format for all its instructions. Variable-sized opcodes are permitted. There are three different types of instructions; M-type, R-type, and C-type. Each M-type instruction has 2 register operands and a 6 -bit immediate operand. Each R-type instruction has 3 register operands. Each C-type instruction has a register operand and a 6-bit offset value. If there are 2 unique M-type opcodes and 7 unique R-type opcodes, which one of the following options gives the maximum number of unique opcodes possible for C-type instructions?

A

8

B

4

C

64

D

16