1
GATE CSE 2024 Set 2
Numerical
+2
-0

A processor uses a 32-bit instruction format and supports byte-addressable memory access. The ISA of the processor has 150 distinct instructions. The instructions are equally divided into two types, namely R-type and I-type, whose formats are shown below.

R-type Instruction Format:

OPCODEUNUSEDDST RegisterSRC Register1SRC Register2

I-type Instruction Format:

OPCODEDST RegisterSRC Register# Immediate value/address

In the OPCODE, 1 bit is used to distinguish between I-type and R-type instructions and the remaining bits indicate the operation. The processor has 50 architectural registers, and all register fields in the instructions are of equal size.

Let X be the number of bits used to encode the UNUSED field, Y be the number of bits used to encode the OPCODE field, and Z be the number of bits used to encode the immediate value/address field. The value of X + 2Y + Z is __________.

Your input ____
2
GATE CSE 2024 Set 2
MCQ (Single Correct Answer)
+2
-0.66

You are given a set $V$ of distinct integers. A binary search tree $T$ is created by inserting all elements of $V$ one by one, starting with an empty tree. The tree $T$ follows the convention that, at each node, all values stored in the left subtree of the node are smaller than the value stored at the node. You are not aware of the sequence in which these values were inserted into $T$, and you do not have access to $T$.

Which one of the following statements is TRUE?

A

Inorder traversal of $T$ can be determined from $V$

B

Root node of $T$ can be determined from $V$

C

Preorder traversal of $T$ can be determined from $V$

D

Postorder traversal of $T$ can be determined from $V$

3
GATE CSE 2024 Set 2
MCQ (Single Correct Answer)
+2
-0.66

Consider the following expression: $x[i] = (p + r) * -s[i] + \frac{u}{w}$. The following sequence shows the list of triples representing the given expression, with entries missing for triples (1), (3), and (6).

(0) + p r
(1)
(2) uminus (1)
(3)
(4) / u w
(5) + (3)(4)
(6)
(7) = (6)(5)

Which one of the following options fills in the missing entries CORRECTLY?

A

(1) = [] s i     (3) * (0) (2)     (6) []= x i

B

(1) []= s i     (3) - (0) (2)     (6) =[] x (5)

C

(1) =[] s i     (3) * (0) (2)     (6) []= x (5)

D

(1) []= s i     (3) - (0) (2)     (6) =[] x i

4
GATE CSE 2024 Set 2
MCQ (More than One Correct Answer)
+2
-0

Let S1 and S2 be two stacks. S1 has capacity of 4 elements. S2 has capacity of 2 elements. S1 already has 4 elements: 100, 200, 300, and 400, whereas S2 is empty, as shown below.

Stack S1
400 (Top)
300
200
100
Stack S2

Only the following three operations are available:

PushToS2: Pop the top element from S1 and push it on S2.
PushToS1: Pop the top element from S2 and push it on S1.
GenerateOutput: Pop the top element from S1 and output it to the user.

Note that the pop operation is not allowed on an empty stack and the push operation is not allowed on a full stack.

Which of the following output sequences can be generated by using the above operations?

A

100, 200, 400, 300

B

200, 300, 400, 100

C

400, 200, 100, 300

D

300, 200, 400, 100

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