1
GATE CSE 2024 Set 1
Numerical
+2
-0

Consider the entries shown below in the forwarding table of an IP router. Each entry consists of an IP prefix and the corresponding next hop router for packets whose destination IP address matches the prefix. The notation “/N” in a prefix indicates a subnet mask with the most significant N bits set to 1.

PrefixNext hop router
10.1.1.0/24R1
10.1.1.128/25R2
10.1.1.64/26R3
10.1.1.192/26R4

This router forwards 20 packets each to 5 hosts. The IP addresses of the hosts are 10.1.1.16, 10.1.1.72, 10.1.1.132, 10.1.1.191, and 10.1.1.205 . The number of packets forwarded via the next hop router R2 is _______

Your input ____
2
GATE CSE 2024 Set 1
Numerical
+2
-0

Consider sending an IP datagram of size 1420 bytes (including 20 bytes of IP header) from a sender to a receiver over a path of two links with a router between them. The first link (sender to router) has an MTU (Maximum Transmission Unit) size of 542 bytes, while the second link (router to receiver) has an MTU size of 360 bytes.

The number of fragments that would be delivered at the receiver is ______________

Your input ____
3
GATE CSE 2024 Set 1
MCQ (Single Correct Answer)
+1
-0.33

Which one of the following statements is FALSE?

A

In the cycle stealing mode of DMA, one word of data is transferred between an I/O device and main memory in a stolen cycle

B

For bulk data transfer, the burst mode of DMA has a higher throughput than the cycle stealing mode

C

Programmed I/O mechanism has a better CPU utilization than the interrupt driven I/O mechanism

D

The CPU can start executing an interrupt service routine faster with vectored interrupts than with non-vectored interrupts

4
GATE CSE 2024 Set 1
MCQ (More than One Correct Answer)
+1
-0

Consider a 5-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of the following statements about forwarding is/are CORRECT?

A

In a pipelined execution, forwarding means the result from a source stage of an earlier instruction is passed on to the destination stage of a later instruction

B

In forwarding, data from the output of the MEM stage can be passed on to the input of the EX stage of the next instruction

C

Forwarding cannot prevent all pipeline stalls

D

Forwarding does not require any extra hardware to retrieve the data from the pipeline stages

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