GATE CSE 2022 | GATE CSE Year Wise Previous Years Questions

GATE CSE 2022

MCQ (More than One Correct Answer)

-0.67

Which of the following is/are the eigenvector(s) for the matrix given below?

$$\left( {\matrix{ { - 9} & { - 6} & { - 2} & { - 4} \cr { - 8} & { - 6} & { - 3} & { - 1} \cr {20} & {15} & 8 & 5 \cr {32} & {21} & 7 & {12} \cr } } \right)$$

$$\left( {\matrix{ { - 1} \cr 1 \cr 0 \cr 1 \cr } } \right)$$

$$\left( {\matrix{ 1 \cr 0 \cr { - 1} \cr 0 \cr } } \right)$$

$$\left( {\matrix{ { - 1} \cr 0 \cr 2 \cr 2 \cr } } \right)$$

$$\left( {\matrix{ 0 \cr 1 \cr { - 3} \cr 0 \cr } } \right)$$

GATE CSE 2022

MCQ (Single Correct Answer)

-0.33

Consider the following threads, T₁, T₂ and T₃ executing on a single processor, synchronized using three binary semaphore variables, S₁, S₂ and S₃, operated upon using standard wait( ) and signal( ). The threads can be context switched in any order and at any time.

$${T_1}$$	$${T_2}$$	$${T_3}$$
while (true) { wait ($${S_3}$$); print ("C"); signal ($${S_2}$$); }	while (true) { wait ($${S_1}$$); print ("B"); signal ($${S_3}$$); }	while (true) { wait ($${S_2}$$); print ("A") signal ($${S_1}$$); }

Which initialization of the semaphores would print the sequence BCABCABCA....... ?

S₁ = 1; S₂ = 1; S₃ = 1

S₁ = 1; S₂ = 1; S₃ = 0

S₁ = 1; S₂ = 0; S₃ = 0

S₀ = 1; S₂ = 1; S₃ = 1

GATE CSE 2022

MCQ (More than One Correct Answer)

-0.33

Which of the following statements is/are TRUE with respect to deadlocks?

Circular wait is a necessary condition for the formation of deadlock.

In a system where each resource has more than one instance, a cycle in its wait for graph indicates the presence of a deadlock.

If the current allocation of resources to processes leads the system to unsafe state, then deadlock will necessarily occur.

In the resource-allocation graph of a system, if every edge is an assignment edge, then the system is not in deadlock state.

GATE CSE 2022

MCQ (Single Correct Answer)

-0.67

Which one of the following statements is FALSE?

The TLB performs an associative search in parallel on all its valid entries using page number of incoming virtual address.

If the virtual address of a word given by CPU has a TLB hit, but the subsequent search for the word results in a cache miss, then the word will always be present in the main memory.

The memory access time using a given inverted page table is always same for all incoming virtual addresses.

In a system that uses hashed page tables, if two distinct virtual addresses V1 and V2 map to the same value while hashing, then the memory access time of these addresses will not be the same.

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