1
GATE CSE 2022
MCQ (Single Correct Answer)
+1
-0.33

Consider the following threads, T1, T2 and T3 executing on a single processor, synchronized using three binary semaphore variables, S1, S2 and S3, operated upon using standard wait( ) and signal( ). The threads can be context switched in any order and at any time.

$${T_1}$$ $${T_2}$$ $${T_3}$$
while (true) {
wait ($${S_3}$$);
print ("C");
signal ($${S_2}$$); }
while (true) {
wait ($${S_1}$$);
print ("B");
signal ($${S_3}$$); }
while (true) {
wait ($${S_2}$$);
print ("A")
signal ($${S_1}$$); }

Which initialization of the semaphores would print the sequence BCABCABCA....... ?

A
S1 = 1; S2 = 1; S3 = 1
B
S1 = 1; S2 = 1; S3 = 0
C
S1 = 1; S2 = 0; S3 = 0
D
S0 = 1; S2 = 1; S3 = 1
2
GATE CSE 2022
MCQ (More than One Correct Answer)
+1
-0.33

Which of the following statements is/are TRUE with respect to deadlocks?

A
Circular wait is a necessary condition for the formation of deadlock.
B
In a system where each resource has more than one instance, a cycle in its wait for graph indicates the presence of a deadlock.
C
If the current allocation of resources to processes leads the system to unsafe state, then deadlock will necessarily occur.
D
In the resource-allocation graph of a system, if every edge is an assignment edge, then the system is not in deadlock state.
3
GATE CSE 2022
MCQ (Single Correct Answer)
+1
-0.33

Which one of the following statements is FALSE?

A
The TLB performs an associative search in parallel on all its valid entries using page number of incoming virtual address.
B
If the virtual address of a word given by CPU has a TLB hit, but the subsequent search for the word results in a cache miss, then the word will always be present in the main memory.
C
The memory access time using a given inverted page table is always same for all incoming virtual addresses.
D
In a system that uses hashed page tables, if two distinct virtual addresses V1 and V2 map to the same value while hashing, then the memory access time of these addresses will not be the same.
4
GATE CSE 2022
MCQ (Single Correct Answer)
+1
-0.33

Consider four processes P, Q, R and S scheduled on a CPU as per round robin algorithm with a time quantum of 4 units. The processes arrive in the order P, Q, R, S, all at time t = 0. There is exactly one context switch from S to Q, exactly one context switch from R to Q, and exactly two context switches from Q to R. There is no context switch from S to P. Switching to a ready process after the termination of another process is also considered a context switch. Which one of the following is NOT possible as CPU burst time (in time units) of these processes?

A
P = 4, Q = 10, R = 6, S = 2
B
P = 2, Q = 9, R = 5, S = 1
C
P = 4, Q = 12, R = 5, S = 4
D
P = 3, Q = 7, R = 7, S = 3
EXAM MAP
Medical
NEET
Graduate Aptitude Test in Engineering
GATE CSEGATE ECEGATE EEGATE MEGATE CEGATE PIGATE IN
Civil Services
UPSC Civil Service
CBSE
Class 12