1
Numerical

GATE CSE 2016 Set 2

Consider a processor with $64$ registers and an instruction set of size twelve. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one destination register identifier, and a twelve-bit immediate value. Each instruction must be stored in memory in a byte-aligned fashion. If a program has $100$ instructions, the amount of memory (in bytes) consumed by the program text is _____________.

2
Numerical

GATE CSE 2016 Set 2

The width of the physical address on a machine is $40$ bits. The width of the tag field in a $512$ $KB$ $8$-way set associative cache is _____________ bits.

3
Numerical

GATE CSE 2016 Set 2

Consider a $3$ $GHz$ (gigahertz) processor with a three-stage pipeline and stage latencies ${\tau _1},{\tau _2},$ and ${\tau _3}$ such that ${\tau _1} = 3{\tau _2}/4 = 2{\tau _3}.$ If the longest pipeline stage is split into two pipeline stages of equal latency, the new frequency is ____________ $GHz,$ ignoring delays in the pipeline registers.

Correct answer is between 3.9 and 4.1
4
Numerical

GATE CSE 2016 Set 2

A file system uses an in-memory cache to cache disk blocks. The miss rate of the cache is shown in the figure. The latency to read a block from the cache is $1$ $ms$ and to read a block from the disk is $10$ $ms.$ Assume that the cost of checking whether a block exists in the cache is negligible. Available cache sizes are in multiples of $10$ $MB.$

The smallest cache size required to ensure an average read latency of less than $6$ $ms$ is _________ $MB.$

Paper Analysis of GATE CSE 2016 Set 2

Subject NameTotal Questions
Algorithms5
Compiler Design3
Computer Networks6
Computer Organization6
Data Structures5
Database Management System4
Digital Logic3
Discrete Mathematics11
Operating Systems3
Theory of Computation6
General Aptitude10