1
GATE CSE 2013
MCQ (Single Correct Answer)
+1
-0.3
The transport layer protocols used for real time multimedia, file transfer, DNS and email, respectively are
A
TCP, UDP, UDP and TCP
B
UDP, TCP, TCP and UDP
C
UDP, TCP, UDP and TCP
D
TCP, UDP, TCP and UDP
2
GATE CSE 2013
MCQ (Single Correct Answer)
+1
-0.3
Using public key cryptography, X adds a digital signature σ to message M, encrypts, and sends it to Y, where it is decrypted. Which one of the following sequences of keys is used for the operations?
A
Encryption: X's private key followed by Y's private key;
Decryption: X’s public key followed by Y’s public key
B
Encryption: X's private key followed by Y's public key;
Decryption: X's public key followed by Y's private key
C
Encryption: X's public key followed by Y's private key;
Decryption: Y's public key followed by X's private key
D
Encryption: X's private key followed by Y's public key;
Decryption: Y's private key followed by X's public key
3
GATE CSE 2013
MCQ (Single Correct Answer)
+2
-0.6
Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction $$(FI),$$ Decode Instruction $$(DI),$$ Fetch Operand $$(FO),$$ Execute Instruction $$(EI)$$ and Write Operand $$(WO).$$ The stage delays for $$FI, DI, FO, EI$$ and $$WO$$ are $$5$$ $$ns,$$ $$7$$ $$ns,$$ $$10$$ $$ns,$$ $$8$$ $$ns$$ and $$6$$ $$ns$$, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is $$1$$ $$ns.$$ A program consisting of $$12$$ instructions $${{\rm I}_1},{{\rm I}_2},{{\rm I}_3},......,\,\,{{\rm I}_{12}}$$ is executed in this pipelined processor. Instruction $${{\rm I}_4}$$ is the only branch instruction and its branch target is $${{\rm I}_9}$$. If the branch is taken during the execution of this program, the time (in $$ns$$) needed to complete the program is
A
$$132$$
B
$$165$$
C
$$176$$
D
$$328$$
4
GATE CSE 2013
MCQ (Single Correct Answer)
+2
-0.6
Consider a hypothetical processor with an instruction of type $$LW$$ $$R1, 20(R2),$$ which during execution reads a $$32$$-bit word from memory and stores it in a $$32$$-bit register $$R1.$$ The effective address of the memory location is obtained by the addition of a constant $$20$$ and the contents of register $$R2.$$ Which of the following best reflects the addressing mode implemented by this instruction for the operand in memory?

A
Immediate Addressing
B
Register Addressing
C
Register Indirect Scaled Addressing
D
Base or Indexed Addressing