Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction $$(FI),$$ Decode Instruction $$(DI),$$ Fetch Operand $$(FO),$$ Execute Instruction $$(EI)$$ and Write Operand $$(WO).$$ The stage delays for $$FI, DI, FO, EI$$ and $$WO$$ are $$5$$ $$ns,$$ $$7$$ $$ns,$$ $$10$$ $$ns,$$ $$8$$ $$ns$$ and $$6$$ $$ns$$, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is $$1$$ $$ns.$$ A program consisting of $$12$$ instructions $${{\rm I}_1},{{\rm I}_2},{{\rm I}_3},......,\,\,{{\rm I}_{12}}$$ is executed in this pipelined processor. Instruction $${{\rm I}_4}$$ is the only branch instruction and its branch target is $${{\rm I}_9}$$. If the branch is taken during the execution of this program, the time (in $$ns$$) needed to complete the program is

Consider a hypothetical processor with an instruction of type $$LW$$ $$R1, 20(R2),$$ which during execution reads a $$32$$-bit word from memory and stores it in a $$32$$-bit register $$R1.$$ The effective address of the memory location is obtained by the addition of a constant $$20$$ and the contents of register $$R2.$$ Which of the following best reflects the addressing mode implemented by this instruction for the operand in memory?

Consider the following sequence of micro-operations
$$\eqalign{ & \,\,\,\,\,\,\,\,\,\,\,\,\,MBR\,\,\,\,\,\,\, \leftarrow PC \cr & \,\,\,\,\,\,\,\,\,\,\,\,\,MAR\,\,\,\,\,\,\, \leftarrow X \cr & \,\,\,\,\,\,\,\,\,\,\,\,\,PC\,\,\,\,\,\,\,\,\,\,\,\, \leftarrow Y \cr & \,\,\,\,\,\,\,\,\,\,\,\,\,Memory\, \leftarrow MBR \cr} $$

Which one of the following is a possible operation performed by this sequence?

The preorder traversal sequence of a binary search tree is 30, 20, 10, 15, 25, 23, 39, 35, 42. Which one of the following is the postorder traversal sequence of the same tree?