1
GATE CSE 2013
MCQ (Single Correct Answer)
+1
-0.3
Using public key cryptography, X adds a digital signature σ to message M, encrypts, and sends it to Y, where it is decrypted. Which one of the following sequences of keys is used for the operations?
A
Encryption: X's private key followed by Y's private key;
Decryption: X’s public key followed by Y’s public key
B
Encryption: X's private key followed by Y's public key;
Decryption: X's public key followed by Y's private key
C
Encryption: X's public key followed by Y's private key;
Decryption: Y's public key followed by X's private key
D
Encryption: X's private key followed by Y's public key;
Decryption: Y's private key followed by X's public key
2
GATE CSE 2013
MCQ (Single Correct Answer)
+1
-0.3
In a $$k$$-way set associative cache, the cache is divided into $$v$$ sets, each of which consists of $$k$$ lines. The lines of a set are placed in sequence one after another. The lines in set $$s$$ are sequenced before the lines in set $$(s+1).$$ The main memory blocks are numbered $$0$$ onwards. The main memory block numbered $$j$$ must be mapped to any one of the cache lines from
A
$${\left( {j\,\,\bmod \,\,v} \right)^ * }k\,\,$$ to $${\left( {j\,\,\bmod \,\,v} \right)^ * }k\, + \,\,\,\,\,\,\left( {k - 1} \right)$$
B
$${\left( {j\,\,\bmod \,\,v} \right)}\,\,$$ to $$\left( {j\,\,\bmod \,\,v} \right)\, + \,\left( {k - 1} \right)$$
C
$${\left( {j\,\,\bmod \,\,k} \right) }\,\,$$ to $$\left( {j\,\,\bmod \,\,k} \right)\, + \,\left( {v - 1} \right)$$
D
$${\left( {j\,\,\bmod \,\,k} \right)^ * }v\,\,$$ to $${\left( {j\,\,\bmod \,\,k} \right)^ * }\,v + \,\left( {v - 1} \right)$$
3
GATE CSE 2013
MCQ (Single Correct Answer)
+2
-0.6
A $$RAM$$ chip has a capacity of $$1024$$ words of $$8$$ bits each $$\left( {1K \times 8} \right).$$ The number of $$2 \times 4$$ decoders with enable line needed to construct a $$16K \times 16\,\,RAM$$ from $$1K \times 8\,\,RAM$$ is
A
$$4$$
B
$$5$$
C
$$6$$
D
$$7$$
4
GATE CSE 2013
MCQ (Single Correct Answer)
+2
-0.6
Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction $$(FI),$$ Decode Instruction $$(DI),$$ Fetch Operand $$(FO),$$ Execute Instruction $$(EI)$$ and Write Operand $$(WO).$$ The stage delays for $$FI, DI, FO, EI$$ and $$WO$$ are $$5$$ $$ns,$$ $$7$$ $$ns,$$ $$10$$ $$ns,$$ $$8$$ $$ns$$ and $$6$$ $$ns$$, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is $$1$$ $$ns.$$ A program consisting of $$12$$ instructions $${{\rm I}_1},{{\rm I}_2},{{\rm I}_3},......,\,\,{{\rm I}_{12}}$$ is executed in this pipelined processor. Instruction $${{\rm I}_4}$$ is the only branch instruction and its branch target is $${{\rm I}_9}$$. If the branch is taken during the execution of this program, the time (in $$ns$$) needed to complete the program is
A
$$132$$
B
$$165$$
C
$$176$$
D
$$328$$
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