1
GATE CSE 2007
MCQ (Single Correct Answer)
+2
-0.6
The message 11001001 is to be transmitted using the CRC polynomial x3 + 1 to protect it from errors. The message that should be transmitted is:
2
GATE CSE 2007
MCQ (Single Correct Answer)
+2
-0.6
There are n stations in a slotted LAN. Each station attempts to transmit with a probability p in each time slot. What is the probability that ONLY one station transmits in a given time slot?
3
GATE CSE 2007
MCQ (Single Correct Answer)
+1
-0.3
In Ethernet when Manchester encoding is used, the bit rate is:
4
GATE CSE 2007
MCQ (Single Correct Answer)
+2
-0.6
Consider a pipelined processor with the following four stages
$$\,\,\,\,\,$$$$IF:$$ Instruction Fetch
$$\,\,\,\,\,$$$$ID:$$ Instruction Decode and Operand Fetch
$$\,\,\,\,\,$$$$EX:$$ Execute
$$\,\,\,\,\,$$$$WB:$$ Write Back
$$\,\,\,\,\,$$$$IF:$$ Instruction Fetch
$$\,\,\,\,\,$$$$ID:$$ Instruction Decode and Operand Fetch
$$\,\,\,\,\,$$$$EX:$$ Execute
$$\,\,\,\,\,$$$$WB:$$ Write Back
The $$IF, ID$$ and $$WB$$ stages take one clock cycle each to complete the operation. The number of clock cycles for the $$EX$$ stage depends on the instruction. The $$ADD$$ and $$SUB$$ instructions need $$1$$ clock cycle and the $$MUL$$ instruction needs $$3$$ clock cycles in the $$EX$$ stage. Operand forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions?
Paper analysis
Total Questions
Algorithms
12
Compiler Design
5
Computer Networks
10
Computer Organization
5
Data Structures
13
Database Management System
11
Digital Logic
5
Discrete Mathematics
20
Operating Systems
9
Programming Languages
1
Theory of Computation
7
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