Consider a machine with a byte addressable main memory of $${2^{16}}$$ bytes. Assume that a direct mapped data cache consisting of $$32$$ lines of $$64$$ bytes each is used in the system. $$A\,\,50 \times 50$$ two-dimensional array of bytes is stored in the main memory starting from memory location $$1100H.$$ Assume that the data cache is initially empty. The complete array is accessed twice. Assume that the contents of the data cache do not change in between the two accesses.

How many data cache misses will occur in total?

Consider a $$4$$-way set associative cache consisting of $$128$$ lines with a line size of $$64$$ words. The $$CPU$$ generates a $$20$$-bit address of a word in main memory. The numbers of bits in the TAG, LINE and WORD fields are respectively

In a look $$-$$ ahead carry generator, the carry generate function $${G_i}$$ and the carry propagate function $${P_i}$$ for inputs, $${A_i}$$ and $${B_i}$$ are given by: $${P_i} = {A_i} \oplus {B_i}$$ and $${G_i} = {A_i}{B_i}.$$

The expressions for the sum bit $${S_i}$$ and the carry bit $${C_{i + 1}}$$ of the look ahead carry adder are given by $${S_i} = {P_i} \oplus {C_i}$$ and $${C_{i + 1}} = {G_i} + {P_i}{C_i},$$ where $${C_0}$$ is the input carry. Consider a two $$-$$ level logic implementation of the look $$-$$ ahead carry generator. Assume that all $${P_i}$$ and $${G_i}$$ are available for the carry generator circuit and that the $$AND$$ and $$OR$$ gates can have any number of inputs. The number of $$AND$$ gates and $$OR$$ gates needed to implement the look $$-$$ ahead carry generator for a $$4$$-bit adder with $${S_3},\,\,{S_2},\,\,{S_1},\,\,{S_0}$$ and $${C_4}$$ as its outputs are respectively

Consider a hash function that distributes keys uniformly. The hash table size is 20. After hashing of how many keys will the probability that any new key hashed collides with an existing one exceed 0.5.