Instruction cache

Instruction register

Instruction opcode

Translation look aside buffer

is flagged whenever there is carry from sign bit addition

cannot occur when $$a$$ $$+$$ $$ve$$ value is added to $$a$$ $$-$$ $$ve$$ value

is flagged when the carries from sign bit and previous bit match

None of the above

The pipeline stages have different delays

Consecutive instructions are depend on each other

The pipeline stages share single hardware resources

All of the above

does not require use of signal decoders.

Results in larger sized micro instructions then vertical micro programming

Uses one bit for each control signal

All of the above