Instruction cache

Instruction register

Instruction opcode

Translation look aside buffer

Floating point multiplication

Signed $$16$$ bit integer addition

Arithmetic left shift

Converting a signed integer from one size to another

The pipeline stages have different delays

Consecutive instructions are depend on each other

The pipeline stages share single hardware resources

All of the above

is flagged whenever there is carry from sign bit addition

cannot occur when $$a$$ $$+$$ $$ve$$ value is added to $$a$$ $$-$$ $$ve$$ value

is flagged when the carries from sign bit and previous bit match

None of the above