The pipeline stages have different delays

Consecutive instructions are depend on each other

The pipeline stages share single hardware resources

All of the above

Instruction cache

Instruction register

Instruction opcode

Translation look aside buffer

the operand is inside the instruction

the address of the operand is inside the instruction

the register containing the address of the operand is specified inside the instruction

the location of the operand is implicit

does not require use of signal decoders.

Results in larger sized micro instructions then vertical micro programming

Uses one bit for each control signal

All of the above