1
GATE CSE 2026 Set 1
Numerical
+2
-0

Let $X$ be a random variable which takes values in the set $\{1,2,3,4,5,6,7,8\}$.

Further, $\operatorname{Pr}(X=1)=\operatorname{Pr}(X=2)=\operatorname{Pr}(X=5)=\operatorname{Pr}(X=7)=\frac{1}{6}$ and $\operatorname{Pr}(X=3)=\operatorname{Pr}(X=4) =\operatorname{Pr}(X=6)=\operatorname{Pr}(X=8)=\frac{1}{12}$.

The expected value of $X$, denoted by $E[X]$, is equal to $\_\_\_\_$ . (rounded off to two decimal places)

Your input ____
2
GATE CSE 2026 Set 1
MCQ (More than One Correct Answer)
+1
-0

With respect to deadlocks in an operating system, which of the following statements is/are FALSE?

A

Banker's algorithm is used to prevent deadlocks

B

Deadlock formation can be prevented by ensuring that the hold and wait condition is not allowed

C

An assignment edge in a resource allocation graph is marked from a process to a resource

D

A safe state guarantees that all processes can finish without formation of a deadlock

3
GATE CSE 2026 Set 1
Numerical
+1
-0

Consider a system consisting of $k$ instances of a resource $R$, being shared by 5 processes. Assume that each process requires a maximum of two instances of resource $R$ and a process can request or release only one instance at a time. Further, a process can request the second instance of the resource only after acquiring the first instance. The minimum value of K for the system to be deadlock-free is $\_\_\_\_$ . (answer in integer)

Your input ____
4
GATE CSE 2026 Set 1
MCQ (More than One Correct Answer)
+2
-0

Consider a system that has a cache memory unit and a memory management unit (MMU). The address input to the cache memory is a physical address. The MMU has a translation lookaside buffer (TLB). Assume that when a page is evicted from the main memory, the corresponding blocks in the cache are marked as invalid.

For a given memory reference, which of the following sequences of events can NEVER happen?

A

TLB miss, Page table hit, Cache hit

B

TLB hit, Page table miss, Cache hit

C

TLB miss, Page table miss, Cache hit

D

TLB miss, Page table miss, Cache miss