Which one of the following dependencies among the register operands of different instructions can cause a data hazard in a pipelined processor?

Consider the real valued variables $X, Y$ and $Z$ represented using the IEEE 754 singleprecision floating-point format. The binary representations of $X$ and $Y$ in hexadecimal notation are as follows:

$$ X: 35 C 00000 \quad Y: 34 A 00000 $$

Let $Z=X+Y$.

Which one of the following is the binary representation of $Z$, in hexadecimal notation?

The size of the physical address space of a processor is $2^{32}$ bytes. The capacity of a cache memory unit is $2^{23}$ bytes. The cache block size is 128 bytes. The cache memory unit can be built as a direct mapped cache or as a $K$-way set-associative cache, where $K=2^L$ and $L \in\{1,2,3\}$. Let the length of the TAG field be $M$ bits for the direct mapped cache, and $N$ bits for the set-associative cache.

Which one of the following options is true?

The EX stage of a pipelined processor performs the memory read operations for LOAD instructions, and the operations for the arithmetic and logic instructions. Let $t_{E X}$ denote the time taken by the EX stage to perform the operation for an instruction. For each instruction type, the values of $t_{E X}$ and $M$ (the number of instructions of that type in a sequence of 100 instructions for a program $P$ ), are given in the table below. The duration of the pipeline clock cycle is 1 nanosecond. Assume that the latch time for the interstage buffers in the pipeline is negligible.

When program $P$ is executed, the number of clock cycles for which the pipeline is stalled due to structural hazards in the EX stage is $\_\_\_\_$ . (answer in integer)