Consider a processor P whose instruction set architecture is the load-store architecture. The instruction format is such that the first operand of any instruction is the destination operand.

Which one of the following sequences of instructions corresponds to the high-level language statement $Z=X+Y$ ?

Note: $X, Y$, and $Z$ are memory operands. $R 0, R 1$, and $R 2$ are registers.

Which one of the following dependencies among the register operands of different instructions can cause a data hazard in a pipelined processor?

Consider the real valued variables $X, Y$ and $Z$ represented using the IEEE 754 singleprecision floating-point format. The binary representations of $X$ and $Y$ in hexadecimal notation are as follows:

$$ X: 35 C 00000 \quad Y: 34 A 00000 $$

Let $Z=X+Y$.

Which one of the following is the binary representation of $Z$, in hexadecimal notation?

The size of the physical address space of a processor is $2^{32}$ bytes. The capacity of a cache memory unit is $2^{23}$ bytes. The cache block size is 128 bytes. The cache memory unit can be built as a direct mapped cache or as a $K$-way set-associative cache, where $K=2^L$ and $L \in\{1,2,3\}$. Let the length of the TAG field be $M$ bits for the direct mapped cache, and $N$ bits for the set-associative cache.

Which one of the following options is true?