1
GATE CSE 2026 Set 1
MCQ (Single Correct Answer)
+2
-0

Consider the implementation of sliding window protocol over a lossless link, with a window size of $W$ frames, where each frame is of size 1000 bits (including header). The bandwidth of the link is $100 \mathrm{kbps}\left(1 \mathrm{k}=10^3\right)$ and the one-way propagation delay is 100 milliseconds. Assume that processing times at the sender and receiver are zero and the transmission time of acknowledgements is also zero. Which one of the following options gives the minimum size of $W$ (in number of frames) required to achieve $100 \%$ link utilization?

A

10

B

21

C

20

D

11

2
GATE CSE 2026 Set 1
MCQ (More than One Correct Answer)
+2
-0

An ISP having an address block 202.16.0.0/15 assigns a block of 6000 IP addresses to a client, using the classless internet domain routing (CIDR) super-netting approach. Which of the following address blocks can be assigned by the ISP?

A

$202.16 .0 .0 / 19$

B

$202.17 .64 .0 / 19$

C

202.16.32.0/19

D

202.17.24.0/19

3
GATE CSE 2026 Set 1
MCQ (Single Correct Answer)
+1
-0

Match each addressing mode in List I with a data element or an element of a data structure (in a high-level language) in List II:

List-I List-II
P. Immediate 1. Element of an array
Q. Indirect 2. Pointer
R. Base with index 3. Element of a record
S. Base with offset/displacement 4. Constant
A

$\mathrm{P}-4, \mathrm{Q}-3, \mathrm{R}-1, \mathrm{~S}-2$

B

$P-4, Q-2, R-1, S-3$

C

$P-1, Q-4, R-3, S-2$

D

$\mathrm{P}-2, \mathrm{Q}-3, \mathrm{R}-1, \mathrm{~S}-4$

4
GATE CSE 2026 Set 1
MCQ (Single Correct Answer)
+1
-0

Consider a processor P whose instruction set architecture is the load-store architecture. The instruction format is such that the first operand of any instruction is the destination operand.

Which one of the following sequences of instructions corresponds to the high-level language statement $Z=X+Y$ ?

Note: $X, Y$, and $Z$ are memory operands. $R 0, R 1$, and $R 2$ are registers.

A

ADD Z, X, Y

B

ADD RO, X, Y STORE Z, R0

C

LOAD RO, X

ADD Z, RO, Y

D

LOAD RO, X

LOAD R1, Y

ADD R2, R0, R1

STORE Z, R2