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1

GATE CSE 2015 Set 2

Numerical
Assume that for a certain processor, a read request takes $$50$$ nanoseconds on a cache miss and $$5$$ nanoseconds on a cache hit. Suppose while running a program, it was observed that $$80\% $$ of the processor's read requests result in a cache hit. The average read access time in nanoseconds is __________.
Your Input ________

Answer

Correct Answer is 14
2

GATE CSE 2015 Set 2

Numerical
Consider a typical disk that rotates at $$15000$$ rotations per minute $$(RPM)$$ and has a transfer rate of $$50 \times {10^6}\,\,\,bytes/\sec .$$ If the average seek time of the disk is twice the average rotational delay and the controller’s transfer time is $$10$$ times the disk transfer time, the average time (in milliseconds) to read or write a $$512$$-byte sector of the disk is ______________________.
Your Input ________

Answer

Correct answer is between 6.1 and 6.2
3

GATE CSE 2015 Set 2

Numerical
Consider the sequence of machine instructions given below:

MUL R5, R0, R1
DIV R6, R2, R3
ADD R7, R5, R6
SUB R8, R7, R4

In the above sequence, $$R0$$ to $$R8$$ are general purpose registers. In the instructions shown, the first register stores the result of the operation performed on the second and the third registers. This sequence of instructions is to be executed in a pipelined instruction processor with the following $$4$$ stages: $$(1)$$ Instruction Fetch and Decode $$(IF), (2)$$ Operand Fetch $$(OF), (3)$$ Perform Operation $$(PO)$$ and $$(4)$$ Write back the result $$(WB).$$ The $$IF,$$ $$OF$$ and $$WB$$ stages take $$1$$ clock cycle each for any instruction. The $$PO$$ stage takes $$1$$ clock cycle for $$ADD$$ or $$SUB$$ instruction, $$3$$ clock cycles for $$MUL$$ instruction and $$5$$ clock cycles for $$DIV$$ instruction. The pipelined processor uses operand forwarding from the $$PO$$ stage to the $$OF$$ stage. The number of clock cycles taken for the execution of the above sequence of instructions is _______________________ .

Your Input ________

Answer

Correct Answer is 13
4

GATE CSE 2015 Set 2

MCQ (Single Correct Answer)
Consider a processor with byte-addressable memory. Assume that all registers, including Program Counter $$(PC)$$ and Program Status Word $$(PSW),$$ are of size $$2$$ bytes. A stack in the main memory is implemented from memory location $${\left( {0100} \right)_{16}}$$ and it grows upward. The stack pointer $$(SP)$$ points to the top element of the stack. The current value of $$SP$$ is $${\left( {016E} \right)_{16}}$$. The CALL instruction is of two words, the first word is the op-code and the second word is the starting address of the subroutine (one word $$= 2$$ bytes). The CALL instruction is implemented as follows:

$$ \bullet \,\,\,\,\,\,\,\,$$ Store the current value of $$PC$$ in the stack
$$ \bullet \,\,\,\,\,\,\,\,$$ Store the value of $$PSW$$ register in the stack
$$ \bullet \,\,\,\,\,\,\,\,$$ Load the starting address of the subroutine in $$PC$$

The content of $$PC$$ just before the fetch of a CALL instruction is $$\left( {5FA0} \right){\,_{16}}.$$ After execution of the CALL instruction, the value of the stack pointer is

A
$$\left( {016A} \right){\,_{16}}$$
B
$$\left( {016C} \right){\,_{16}}$$
C
$$\left( {0170} \right){\,_{16}}$$
D
$$\left( {0172} \right){\,_{16}}$$

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