1
GATE CSE 2015 Set 2
MCQ (Single Correct Answer)
+2
-0.6
Consider the following routing table at an IP router: GATE CSE 2015 Set 2 Computer Networks - Network Layer Question 17 English 1

For each IP address in Group I identify the correct choice of the next hop from Group II using the entries from the routing table above.

GATE CSE 2015 Set 2 Computer Networks - Network Layer Question 17 English 2
A
i - a, ii - c, iii - e, iv - d
B
i - a, ii - d, iii - b, iv - e
C
i - b, ii - c, iii - d, iv - e
D
i - b, ii - c, iii - e, iv - d
2
GATE CSE 2015 Set 2
MCQ (Single Correct Answer)
+1
-0.3
Identify the correct order in which a server process must invoke the function calls accept, bind, listen, and recv according to UNIX socket APL
A
listen, accept, bind recv
B
bind, listen, accept, recv
C
bind, accept, listen, recv
D
accept, listen, bind recv
3
GATE CSE 2015 Set 2
MCQ (Single Correct Answer)
+2
-0.6
Assume that the bandwidth for a TCP connection is 1048560 bits/sec. Let $$\alpha $$ be the value of RTT in milliseconds(rounded off to the nearest integer) after which the TCP window scale option is needed. Let $$\beta $$ be the maximum possible window size the window scale option. Then the values of $$\alpha $$ and $$\beta $$ are
A
63 milliseconds, $$65535 \times {2^{14}}$$
B
63 milliseconds, $$65535 \times {2^{16}}$$
C
500 milliseconds, $$65535 \times {2^{14}}$$
D
63 milliseconds, $$65535 \times {2^{16}}$$
4
GATE CSE 2015 Set 2
Numerical
+2
-0
Consider the sequence of machine instructions given below:

MUL R5, R0, R1
DIV R6, R2, R3
ADD R7, R5, R6
SUB R8, R7, R4

In the above sequence, $$R0$$ to $$R8$$ are general purpose registers. In the instructions shown, the first register stores the result of the operation performed on the second and the third registers. This sequence of instructions is to be executed in a pipelined instruction processor with the following $$4$$ stages: $$(1)$$ Instruction Fetch and Decode $$(IF), (2)$$ Operand Fetch $$(OF), (3)$$ Perform Operation $$(PO)$$ and $$(4)$$ Write back the result $$(WB).$$ The $$IF,$$ $$OF$$ and $$WB$$ stages take $$1$$ clock cycle each for any instruction. The $$PO$$ stage takes $$1$$ clock cycle for $$ADD$$ or $$SUB$$ instruction, $$3$$ clock cycles for $$MUL$$ instruction and $$5$$ clock cycles for $$DIV$$ instruction. The pipelined processor uses operand forwarding from the $$PO$$ stage to the $$OF$$ stage. The number of clock cycles taken for the execution of the above sequence of instructions is _______________________ .

Your input ____
EXAM MAP
Medical
NEETAIIMS
Graduate Aptitude Test in Engineering
GATE CSEGATE ECEGATE EEGATE MEGATE CEGATE PIGATE IN
Civil Services
UPSC Civil Service
Defence
NDA
Staff Selection Commission
SSC CGL Tier I
CBSE
Class 12