Host A sends a UDP datagram containing 8880 bytes of user data to host B over an Ethernet LAN. Ethernet frames may carry data up to 1500 bytes (i.e. MTU = 1500 bytes). Size of UDP header is 8 bytes and size of IP heard is 20 bytes.There is no option field in IP header How many total number of IP fragments will be transmitted and what will be the contents of offset field in the last fragment?

Assume that the bandwidth for a TCP connection is 1048560 bits/sec. Let $$\alpha $$ be the value of RTT in milliseconds(rounded off to the nearest integer) after which the TCP window scale option is needed. Let $$\beta $$ be the maximum possible window size the window scale option. Then the values of $$\alpha $$ and $$\beta $$ are

Consider a typical disk that rotates at $$15000$$ rotations per minute $$(RPM)$$ and has a transfer rate of $$50 \times {10^6}\,\,\,bytes/\sec .$$ If the average seek time of the disk is twice the average rotational delay and the controller’s transfer time is $$10$$ times the disk transfer time, the average time (in milliseconds) to read or write a $$512$$-byte sector of the disk is ______________________.

Consider the sequence of machine instructions given below:

MUL	R5, R0, R1
DIV	R6, R2, R3
ADD	R7, R5, R6
SUB	R8, R7, R4

In the above sequence, $$R0$$ to $$R8$$ are general purpose registers. In the instructions shown, the first register stores the result of the operation performed on the second and the third registers. This sequence of instructions is to be executed in a pipelined instruction processor with the following $$4$$ stages: $$(1)$$ Instruction Fetch and Decode $$(IF), (2)$$ Operand Fetch $$(OF), (3)$$ Perform Operation $$(PO)$$ and $$(4)$$ Write back the result $$(WB).$$ The $$IF,$$ $$OF$$ and $$WB$$ stages take $$1$$ clock cycle each for any instruction. The $$PO$$ stage takes $$1$$ clock cycle for $$ADD$$ or $$SUB$$ instruction, $$3$$ clock cycles for $$MUL$$ instruction and $$5$$ clock cycles for $$DIV$$ instruction. The pipelined processor uses operand forwarding from the $$PO$$ stage to the $$OF$$ stage. The number of clock cycles taken for the execution of the above sequence of instructions is _______________________ .