1
GATE CSE 2012
MCQ (Single Correct Answer)
+1
-0.3
Register renaming is done in pipelined processors
A
as an alternative to register allocation at compile time
B
for efficient access to function parameters and local variables
C
to handle certain kinds of hazards
D
as part of address translation
2
GATE CSE 2012
MCQ (Single Correct Answer)
+2
-0.6
A computer has a $$256$$ $$K$$ Byte, $$4$$-way set associative, write back data cache with block size of $$32$$ Bytes. The processor sends $$32$$ bit addresses to the cache controller. Each cache tag director $$y$$ entry contains, in addition to address tag, $$2$$ valid bits. $$1$$ modified bit and $$1$$ replacement bit.

The number of bit in the tag field of an address is

A
$$11$$
B
$$14$$
C
$$16$$
D
$$27$$
3
GATE CSE 2012
MCQ (Single Correct Answer)
+1
-0.3
The decimal value $$0.5$$ in $$IEEE$$ single precision floating point representation has
A
fraction bits of $$00000…000000$$ and exponent value of $$0$$
B
fraction bits of $$00000…000000$$ and exponent value of $$−1$$
C
fraction bits of $$10000…000000$$ and exponent value of $$0$$
D
no exact representation
4
GATE CSE 2012
MCQ (Single Correct Answer)
+2
-0.6
The height of a tree is defined as the number of edges on the longest path in the tree. The function shown in the pseudocode below is invoked as height (root) to compute the height of a binary tree rooted at the tree pointer root.
int height (treeptr n) 
  { if (n== NULL) return -1; 
  if (n-> left == NULL) 
  if (n-> right ==NULL) return 0; 
  else return B1 ;             // Box 1 
  else {h1 = height (n -> left); 
      if (n -> right == NULL) return (1 + h1); 
      else {h2 = height (n -> right); 
          return B2 ;          // Box 2 
          } 
      } 
}
The appropriate expression for the two boxes B1 and B2 are
A
B1 : (1 + height(n->right)), B2 : (1 + max(h1,h2))
B
B1 : (height(n->right)), B2 : (1 + max(h1,h2))
C
B1 : height(n->right), B2 : max(h1,h2)
D
B1 : height(n->right), B2 : max(h1,h2)