Given a computing system with two levels of cache (L1 and L2) and a main memory. The first level (L1) cache access time is 1 nanosecond (ns) and the "hit rate" for L1 cache is $90 \%$ while the processor is accessing the data from L1 cache. Whereas, for the second level (L2) cache, the "hit rate" is $80 \%$ and the "miss penalty" for transferring data from L2 cache to L1 cache is 10 ns . The "miss penalty" for the data to be transferred from main memory to L2 cache is 100 ns . Then the average memory access time in this system in nanoseconds is (rounded off to one decimal place)
A 5-stage instruction pipeline has stage delays of $180,250,150,170$, and 250 , respectively, in nanoseconds. The delay of an inter-stage latch is 10 nanoseconds. Assume that there are no pipeline stalls due to branches and other hazards. The time taken to process 1000 instructions in microseconds is ________ . (Rounded off to two decimal places)
An application executes $6.4 \times 10^8$ number of instructions in 6.3 seconds. There are four types of instructions, the details of which are given in the table. The duration of a clock cycle in nanoseconds is _________. (rounded off to one decimal place)
| Instruction type |
Clock cycles required per instruction (CPI) |
Number of Instructions executed |
|---|---|---|
| Branch | 2 | $2.25\times10^8$ |
| Load | 5 | $1.20\times10^8$ |
| Store | 4 | $1.65\times10^8$ |
| Arithmetic | 3 | $1.30\times10^8$ |
Consider a binary tree $T$ in which every node has either zero or two children. Let $n>0$ be the number of nodes in $T$. Which ONE of the following is the number of nodes in $T$ that have exactly two children?