1
GATE CSE 2021 Set 2
MCQ (More than One Correct Answer)
+2
-0

Consider a computer network using the distance vector routing algorithm in its network layer. The partial topology of the network is as shown below.

GATE CSE 2021 Set 2 Computer Networks - Network Layer Question 10 English

The objective is to find the shortest-cost path from the router R to routers P and Q. Assume that R does not initially know the shortest routes to P and Q. Assume that R has three neighbouring routers denoted as X, Y, and Z. During one iteration, R measures its distance to its neighbours X, Y, and Z as 3, 2, and 5, respectively. Router R gets routing vectors from its neighbours that indicate that the distance to router P from routers X, Y, and Z are 7, 6, and 5, respectively. The routing vector also indicates that the distance to router Q from routers X, Y, and Z are 4, 6, and 8, respectively. Which of the following statement(s) is/are correct with respect to the new routing table of R, after updation during this iteration ? 

A
The next hop router for a packet from R to P is Y.
B
The distance from R to Q will be stored as 7
C
The next hop router for a packet from R to Q is Z.
D
The distance from R to P will be stored as 10.
2
GATE CSE 2021 Set 2
MCQ (Single Correct Answer)
+2
-0.66
Consider the cyclic redundancy check (CRC) based error detecting scheme having the generator polynomial X3 + X + 1. Suppose the message m4m3m2m1m0 = 11000 is to be transmitted. Check bits c2c1c0 are appended at the end of the message by the transmitter using the above CRC scheme. The transmitted bit string is denoted by m4m3m2m1m0c2c1c0. The value of the check bit sequence c2c1c0 is 
A
101
B
100
C
111
D
110
3
GATE CSE 2021 Set 2
Numerical
+1
-0
Consider a set-associative cache of size 2 KB (1 KB = 210 bytes) with cache block size of 64 bytes. Assume that the cache is byte-addressable and a 32-bit address is used for accessing the cache. If the width of the tag field is 22 bits, the associativity of the cache is _______
Your input ____
4
GATE CSE 2021 Set 2
MCQ (Single Correct Answer)
+2
-0.66

Assume a two-level inclusive cache hierarchy, L1 and L2, where L2 is the larger of the two. Consider the following statements.

S1 : Read misses in a write through L1 cache do not result in writebacks of dirty lines to the L2.

S2 : Write allocate policy must be used in conjunction with write through caches and no-write allocate policy is used with writeback caches.

Which of the following statements is correct? 

A
S1 is true and S2 is true
B
S1 is false and S2 is true
C
S1 is false and S2 is false
D
S1 is true and S2 is false
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