A five-stage pipeline has stage delays of 150, 120, 150, 160 and 140 nanoseconds. The registers that are used between the pipeline stages have a delay of 5 nanoseconds each.
The total time to execute 100 independent instructions on this pipeline, assuming there are no pipeline stalls, is ______ nanoseconds.
Consider the following instruction sequence where register R1, R2 and R3 are general purpose and MEMORY[X] denotes the content at the memory location X.
|
Instruction |
Semantics |
Instruction Size (bytes) |
|
MOV R1, (5000) |
R1 ← MEMORY[5000] |
4 |
|
MOV R2, (R3) |
R2 ← MEMORY[R3] |
4 |
|
ADD R2, R1 |
R2 ← R1 + R2 |
2 |
|
MOV (R3), R2 |
MEMORY[R3] ← R2 |
4 |
|
INC R3 |
R3 ← R3 + 1 |
2 |
|
DEC R1 |
R1 ← R1 – 1 |
2 |
|
BNZ 1004 |
Branch if not zero to the given absolute address |
2 |
|
HALT |
Stop |
1 |
Assume that the content of the memory location 5000 is 10, and the content of the register R3 is 3000. The content of each of the memory locations from 3000 to 3010 is 50. The instruction sequence starts from the memory location 1000. All the numbers are in decimal format. Assume that the memory is byte addressable.
After the execution of the program, the content of memory location 3010 is ______
Consider a computer system with a byte-addressable primary memory of size 232 bytes. Assume the computer system has a direct-mapped cache of size 32 KB (1 KB = 210 bytes), and each cache block is of size 64 bytes.
The size of the tag field is ______ bits.
Consider the following undirected graph with edge weights as shown:
The number of minimum-weight spanning trees of the graph is ______