1
GATE CSE 2021 Set 1
Numerical
+2
-0.67

Consider the sliding window flow-control protocol operating between a sender and a receiver over a full-duplex error-free link. Assume the following:

1. The time taken for processing the data frame by the receiver is negligible.

2. The time taken for processing the acknowledgement frame by the sender is negligible.

3. The sender has infinite number of frames available for transmission.

4. The size of the data frame is 2,000 bits and the size of the acknowledgment frame is 10 bits.

5. The link data rate in each direction is 1 Mbps (= 106 bits per second).

6. One way propagation delay of the link is 100 milliseconds.

The minimum value of the sender's window size in terms of the number of frames, (rounded to the nearest integer) needed to achieve a link utilization of 50% is ______

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2
GATE CSE 2021 Set 1
MCQ (More than One Correct Answer)
+2
-0.67

A TCP server application is programmed to listen on port number P on host S. A TCP client connected to the TCP server over the network.

Consider that while the TCP connection was active, the server machine S crashed are rebooted. Assume that the client does not use the TCP keepalive timer.

Which of the following behaviours is/are possible?

A
If the client sends a packet after the server reboot, it will receive a RST segment.
B
If the client was waiting to receive a packet, it may wait indefinitely.
C
It the client sends a packet after the server reboot, it will receive a FIN segment.
D
The TCP server application on S can listen on P after reboot.
3
GATE CSE 2021 Set 1
MCQ (Single Correct Answer)
+2
-0.67

Consider the following two statements.

S1 : Destination MAC address of an ARP reply is a broadcast address.

S2 : Destination MAC address of an ARP request is a broadcast address.

Which one of the following choices is correct?

A
S1 is tue and S2 is false.
B
Both S1 and S2 are false.
C
S1 is false and S2 is true.
D
Both S1 and S2 are true.
4
GATE CSE 2021 Set 1
Numerical
+2
-0.67

A five-stage pipeline has stage delays of 150, 120, 150, 160 and 140 nanoseconds. The registers that are used between the pipeline stages have a delay of 5 nanoseconds each.

The total time to execute 100 independent instructions on this pipeline, assuming there are no pipeline stalls, is ______ nanoseconds.

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