1
GATE CSE 2014 Set 3
MCQ (Single Correct Answer)
+2
-0.6
Consider the following processors ($$ns$$ stands for nanoseconds). Assume that the pipeline registers have zero latency.
$$P1:$$ Four-stage pipeline with stage latencies $$1$$ $$ns,$$ $$2$$ $$ns,$$ $$2$$ $$ns,$$ $$1$$ $$ns.$$
$$P2:$$ Four-stage pipeline with stage latencies $$1$$ $$ns,$$ 1$$.5$$ $$ns,$$ $$1.5$$ $$ns,$$ $$1.5$$ $$ns.$$
$$P3:$$ Five-stage pipeline with stage latencies $$0.5$$ $$ns,$$ $$1$$ $$ns,$$ $$1$$ $$ns,$$ $$0.6$$ $$ns,$$ $$1$$ $$ns.$$
$$P4:$$ Five-stage pipeline with stage latencies $$0.5$$ $$ns,$$ $$0.5$$ $$ns,$$ $$1$$ $$ns,$$ $$1$$ $$ns,$$ $$1.1$$ $$ns.$$

Which processor has the highest peak clock frequency?

A
$$P1$$
B
$$P2$$
C
$$P3$$
D
$$P4$$
2
GATE CSE 2014 Set 3
Numerical
+2
-0
An instruction pipeline has five stages, namely, instruction fetch $$(IF),$$ instruction decode and register fetch $$(ID/RF)$$ instruction execution $$(EX),$$ memory access $$(MEM),$$ and register writeback $$(WB)$$ with stage latencies $$1$$ ns, $$2.2$$ $$ns,$$ $$2$$ $$ns,$$ $$1$$ $$ns,$$ and $$0.75$$ $$ns,$$ respectively ($$ns$$ stands for nanoseconds). To gain in terms of frequency, the designers have decided to split the $$ID/RF$$ stage into three stages $$(ID, RF1, RF2)$$ each of latency $$2.2/3$$ $$ns,$$ Also, the $$EX$$ stage is split into two stages $$(EX1, EX2)$$ each of latency $$1$$ ns. The new design has a total of eight pipeline stages. A program has $$20$$% branch instructions which execute in the $$EX$$ stage and produce the next instruction pointer at the end of the $$EX$$ stage in the old design and at the end of the $$EX2$$ stage in the new design. The IF stage stalls after fetching a branch instruction until the next instruction pointer is computed. All instructions other than the branch instruction have an average $$CPI$$ of one in both the designs. The execution times of this program on the old and the new design are $$P$$ and $$Q$$ nanoseconds, respectively. The value of $$P/Q$$ is _____________.
Your input ____
3
GATE CSE 2014 Set 3
MCQ (Single Correct Answer)
+1
-0.3
Consider the following rooted tree with the vertex labelled P as the root GATE CSE 2014 Set 3 Data Structures - Trees Question 58 English The order in which the nodes are visited during an in-order traversal of the tree is
A
SQPTRWUV
B
SQPTRUWRV
C
SQPTWUVR
D
SQPTRUWV
4
GATE CSE 2014 Set 3
MCQ (Single Correct Answer)
+2
-0.6
Consider the C function given below. Assume that the array listA contains n (> 0) elements, sored in ascending order.
int ProcessArray(int *listA, int x, int n) 
{ 
      int i, j, k; 
      i = 0; 
      j = n-1; 
      do 
      { 
         k = (i+j)/2; 
         if (x <= listA[k]) 
           j = k-1; 
         if (listA[k] <= x) 
           i = k+1; 
      } 
      while (i <= j); 
      if (listA[k] == x) 
           return(k); 
      else 
           return -1; 
}
Which one of the following statements about the function ProcessArray is CORRECT?
A
It will run into an infinite loop when x is not in listA
B
It is an implementation of binary search.
C
It will always find the maximum element in listA.
D
It will return −1 even when X is present in listA.
EXAM MAP
Medical
NEET
Graduate Aptitude Test in Engineering
GATE CSEGATE ECEGATE EEGATE MEGATE CEGATE PIGATE IN
CBSE
Class 12