1
GATE CSE 2014 Set 3
MCQ (Single Correct Answer)
+2
-0.6
Consider the following processors ($$ns$$ stands for nanoseconds). Assume that the pipeline registers have zero latency.
$$P1:$$ Four-stage pipeline with stage latencies $$1$$ $$ns,$$ $$2$$ $$ns,$$ $$2$$ $$ns,$$ $$1$$ $$ns.$$
$$P2:$$ Four-stage pipeline with stage latencies $$1$$ $$ns,$$ 1$$.5$$ $$ns,$$ $$1.5$$ $$ns,$$ $$1.5$$ $$ns.$$
$$P3:$$ Five-stage pipeline with stage latencies $$0.5$$ $$ns,$$ $$1$$ $$ns,$$ $$1$$ $$ns,$$ $$0.6$$ $$ns,$$ $$1$$ $$ns.$$
$$P4:$$ Five-stage pipeline with stage latencies $$0.5$$ $$ns,$$ $$0.5$$ $$ns,$$ $$1$$ $$ns,$$ $$1$$ $$ns,$$ $$1.1$$ $$ns.$$

Which processor has the highest peak clock frequency?

A
$$P1$$
B
$$P2$$
C
$$P3$$
D
$$P4$$
2
GATE CSE 2014 Set 3
Numerical
+2
-0
An instruction pipeline has five stages, namely, instruction fetch $$(IF),$$ instruction decode and register fetch $$(ID/RF)$$ instruction execution $$(EX),$$ memory access $$(MEM),$$ and register writeback $$(WB)$$ with stage latencies $$1$$ ns, $$2.2$$ $$ns,$$ $$2$$ $$ns,$$ $$1$$ $$ns,$$ and $$0.75$$ $$ns,$$ respectively ($$ns$$ stands for nanoseconds). To gain in terms of frequency, the designers have decided to split the $$ID/RF$$ stage into three stages $$(ID, RF1, RF2)$$ each of latency $$2.2/3$$ $$ns,$$ Also, the $$EX$$ stage is split into two stages $$(EX1, EX2)$$ each of latency $$1$$ ns. The new design has a total of eight pipeline stages. A program has $$20$$% branch instructions which execute in the $$EX$$ stage and produce the next instruction pointer at the end of the $$EX$$ stage in the old design and at the end of the $$EX2$$ stage in the new design. The IF stage stalls after fetching a branch instruction until the next instruction pointer is computed. All instructions other than the branch instruction have an average $$CPI$$ of one in both the designs. The execution times of this program on the old and the new design are $$P$$ and $$Q$$ nanoseconds, respectively. The value of $$P/Q$$ is _____________.
Your input ____
3
GATE CSE 2014 Set 3
MCQ (Single Correct Answer)
+1
-0.3
Consider the following rooted tree with the vertex labelled P as the root GATE CSE 2014 Set 3 Data Structures - Trees Question 58 English The order in which the nodes are visited during an in-order traversal of the tree is
A
SQPTRWUV
B
SQPTRUWRV
C
SQPTWUVR
D
SQPTRUWV
4
GATE CSE 2014 Set 3
MCQ (Single Correct Answer)
+2
-0.6
Consider the pseudocode given below. The function Dosomething () takes as argument a pointer to the root of an arbitrary tree represented by the leftMostChild-rightSibling representation. Each node of the tree is of type treeNode.
typedef struct treeNode* treeptr; 
Struct treeNode 
{ 
    Treeptr leftMostchild, rightSibiling; 
}; 
Int Dosomething (treeptr tree) 
{ 
    int value =0; 
    if (tree ! = NULL) { 
      If (tree -> leftMostchild = = NULL) 
          value=1; 
    else 
        value = Dosomething (tree->leftMostchild); 
        value = value + Dosometing (tree->rightsibiling); 
    } 
    return (value); 
}
When the pointer to the root of a tree is passed as the argument to DoSomething, the value returned by the function corresponds to the
A
number of internal nodes in the tree.
B
height of the tree
C
number of nodes without a right sibling in the tree.
D
number of leaf nodes in the tree.
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