1
GATE CSE 2014 Set 2
MCQ (Single Correct Answer)
+2
-0.6
The value of a float type variable is represented using the single-precision $$32$$-bit floating point format of $$IEEE-754$$ standard that uses $$1$$ bit for sign, $$8$$ bits for biased exponent and $$23$$ bits for mantissa. $$A$$ float type variable $$X$$ is assigned the decimal value of $$−14.25.$$ The representation of $$X$$ in hexadecimal notation is
A
$$C1640000H$$
B
$$416C0000H$$
C
$$41640000H$$
D
$$C16C0000H$$
2
GATE CSE 2014 Set 2
Numerical
+2
-0
A $$4$$-way set-associative cache memory unit with a capacity of $$16KB$$ is built using a block size of $$8$$ words. The word length is $$32$$ bits. The size of the physical address space is $$4$$ $$GB.$$ The number of bit for the TAG field is ____________.
Your input ____
3
GATE CSE 2014 Set 2
MCQ (Single Correct Answer)
+2
-0.6
In designing a computer’s cache system, the cache block (or cache line) size is an important parameter. Which one of the following statements is correct in this context?
A
A smaller block size implies better spatial locality
B
A smaller block size implies a smaller cache tag and hence lower cache tag overhead
C
A smaller block size implies a larger cache tag and hence lower cache hit time
D
A smaller block size incurs a lower cache miss penalty
4
GATE CSE 2014 Set 2
MCQ (Single Correct Answer)
+2
-0.6
If the associativity of a processor cache is doubled while keeping the capacity and block size unchanged, which one of the following is guaranteed to be NOT affected?
A
Width of tag comparator
B
Width of set index decoder
C
Width of way selection multiplexor
D
Width of processor to main memory data bus
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