Which is the most appropriate match for the items in the first column with the items in the second column?
$$X.$$ Indirect Addressing
$$Y.$$ Indexed Addressing
$$Z.$$ Base Register Addressing
$${\rm I}.\,\,$$Array implementation
$${\rm II}.\,\,$$Writing relocatable code
$${\rm III}.\,\,$$Passing array as parameter

A $$CPU$$ has $$32$$-bit memory address and a $$256$$ $$KB$$ cache memory. The cache is organized as a $$4$$-way set associative cache with cache block size of $$16$$ bytes.

(a)$$\,\,\,\,$$ What is the number of sets in the cache?
(b)$$\,\,\,\,$$ What is the size (in bits) of the tag field per cache block?
(c)$$\,\,\,\,$$ What is the number and size of comparators required for tag matching?
(d)$$\,\,\,\,$$ How many address bits are required to find the byte offset within a cache block?
(e)$$\,\,\,\,$$ What is the total amount of extra memory (in bytes) required for the tag bits?

Consider the following datapath of a simple non-pipelined $$CPU.$$ The registers $$A,B,$$ $${A_1},{A_2},$$ $$MDR,$$ the bus and the $$ALU$$ are $$8$$-bit wide. $$SP$$ and $$MAR$$ are $$16$$-bit registers. The $$MUX$$ is of size $$8 \times \left( {2:1} \right)$$ and the $$DEMUX$$ is of size $$8 \times \left( {1:2} \right)$$. Each memory operation takes $$2$$ $$CPU$$ clock cycles and uses $$MAR$$ (Memory Address Register) and $$MDR$$ (Memory Data register). $$SP$$ can be decremented locally.

The $$CPU$$ instruction $$''push$$ $$r'',$$ where $$r=A$$ or $$B,$$ has the specification
$$\eqalign{ & \,\,\,\,\,\,\,\,\,\,\,\,\,M\left[ {SP} \right] \leftarrow r \cr & \,\,\,\,\,\,\,\,\,\,\,\,\,SP \leftarrow SP - 1 \cr} $$
How many $$CPU$$ clock cycles are needed to execute the $$''push$$ $$r''$$ instruction?

Arrange the following configuration for CPU in decreasing order of operating speeds: Hardwired control, vertical micro- programming, horizontal micro-programming