1
GATE CSE 2001
MCQ (Single Correct Answer)
+2
-0.6
Which is the most appropriate match for the items in the first column with the items in the second column?
$$X.$$ Indirect Addressing
$$Y.$$ Indexed Addressing
$$Z.$$ Base Register Addressing
$${\rm I}.\,\,$$Array implementation
$${\rm II}.\,\,$$Writing relocatable code
$${\rm III}.\,\,$$Passing array as parameter
A
$$\left( {X,\,{\rm I}{\rm I}{\rm I}} \right),\,\,\left( {Y,\,{\rm I}} \right),\,\,\left( {Z,\,\,{\rm I}{\rm I}} \right)$$
B
$$\left( {X,\,{\rm I}{\rm I}} \right),\,\,\left( {Y,\,{\rm I}{\rm I}{\rm I}} \right),\,\,\left( {Z,\,\,{\rm I}} \right)$$
C
$$\left( {X,\,{\rm I}{\rm I}{\rm I}} \right),\,\,\left( {Y,\,{\rm I}{\rm I}} \right),\,\,\left( {Z,\,\,{\rm I}} \right)$$
D
$$\left( {X,\,{\rm I}} \right),\,\,\left( {Y,\,{\rm I}{\rm I}{\rm I}} \right),\,\,\left( {Z,\,\,{\rm I}{\rm I}} \right)$$
2
GATE CSE 2001
MCQ (Single Correct Answer)
+2
-0.6
Arrange the following configuration for CPU in decreasing order of operating speeds: Hardwired control, vertical micro- programming, horizontal micro-programming
A
Hardwired control, vertical micro-programming, horizontal micro-programming
B
Hardwired control, horizontal micro- programming, vertical micro-programming
C
Horizontal micro-programming, vertical micro-programming, hardwired control
D
Vertical micro-programming, horizontal micro-programming, hardwired control
3
GATE CSE 2001
MCQ (Single Correct Answer)
+2
-0.6
Consider the following datapath of a simple non-pipelined $$CPU.$$ The registers $$A,B,$$ $${A_1},{A_2},$$ $$MDR,$$ the bus and the $$ALU$$ are $$8$$-bit wide. $$SP$$ and $$MAR$$ are $$16$$-bit registers. The $$MUX$$ is of size $$8 \times \left( {2:1} \right)$$ and the $$DEMUX$$ is of size $$8 \times \left( {1:2} \right)$$. Each memory operation takes $$2$$ $$CPU$$ clock cycles and uses $$MAR$$ (Memory Address Register) and $$MDR$$ (Memory Data register). $$SP$$ can be decremented locally. GATE CSE 2001 Computer Organization - Alu Data Path and Control Unit Question 8 English

The $$CPU$$ instruction $$''push$$ $$r'',$$ where $$r=A$$ or $$B,$$ has the specification
$$\eqalign{ & \,\,\,\,\,\,\,\,\,\,\,\,\,M\left[ {SP} \right] \leftarrow r \cr & \,\,\,\,\,\,\,\,\,\,\,\,\,SP \leftarrow SP - 1 \cr} $$
How many $$CPU$$ clock cycles are needed to execute the $$''push$$ $$r''$$ instruction?

A
$$2$$
B
$$3$$
C
$$4$$
D
$$5$$
4
GATE CSE 2001
MCQ (Single Correct Answer)
+1
-0.3
A processor needs software interrupt to
A
Test the interrupt system of the processor
B
Implement co-routines
C
Obtain system services which need execution of privileged instructions
D
Return from subroutine
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