Suppose a program is running on a non-pipelined single processor computer system. The computer is connected to an external device that can interrupt the processor asynchronously. The processor needs to execute the interrupt service routine (ISR) to serve this interrupt. The following steps (not necessarily in order) are taken by the processor when the interrupt arrives:

(i) The processor saves the content of the program counter.

(ii) The program counter is loaded with the start address of the ISR.

(iii) The processor finishes the present instruction.

Which ONE of the following is the CORRECT sequence of steps?

A partial data path of a processor is given in the figure, where $R A, R B$, and $R Z$ are 32-bit registers. Which option(s) is/are CORRECT related to arithmetic operations using the data path as shown?

Consider a memory system with 1 M bytes of main memory and 16 K bytes of cache memory. Assume that the processor generates 20-bit memory address, and the cache block size is 16 bytes. If the cache uses direct mapping, how many bits will be required to store all the tag values?

[Assume memory is byte addressable, $1 \mathrm{~K}=2^{10}$, $1 \mathrm{M}=2^{20}$]

A processor has 64 general-purpose registers and 50 distinct instruction types. An instruction is encoded in 32-bits. What is the maximum number of bits that can be used to store the immediate operand for the given instruction?

$$\mathrm{ADD ~ R1,~\#25 \qquad // R1 = R1 + 25}$$