1
GATE CSE 1999
MCQ (Single Correct Answer)
+1
-0.3
Suppose that the expectation of a random variable X is 5. Which of the following statements is true?
A
There is a sample point at which X has the value 5.
B
There is a sample point at which X has the value greater than 5.
C
There is a sample point at which X has a value greater than or equal to 5.
D
None of the above.
2
GATE CSE 1999
MCQ (Single Correct Answer)
+1
-0.3
Which of the following disk scheduling strategies is likely to give the best throughput?
A
Farthest cylinder next
B
Nearest cylinder next
C
First come first served
D
Elevator algorithm
3
GATE CSE 1999
MCQ (More than One Correct Answer)
+2
-0
Which of the following is/are advantage of virtual memory?
A
Faster access to memory on an average.
B
Processes can be given protected address spaces.
C
Linker can assign addresses independent of where the program will be loaded in physical memory.
D
Programs larger than the physical memory size can be run.
4
GATE CSE 1999
Subjective
+5
-0
A certain computer system has the segmented paging architecture for virtual memory. The memory is byte addressable. Both virtual and physical address spaces contain $${2^{16}}$$ bytes each. The virtual address space is divided into $$8$$ non-overlapping equal size segments. The memory management unit $$(MMU)$$ has a hardware segment table, each entry of which contains the physical address of the page table for the segment. Page table are stored in the main memory and consists of $$2$$ byte page table entries.

(a)$$\,\,\,\,\,$$ What is the minimum page size in bytes so that the page table for a segment requires at most one page to store it? Assume that the page size can only be a power of $$2.$$

(b)$$\,\,\,\,\,$$ Now suppose that the pages size is $$512$$ bytes. It is proposed to provide a $$TLB$$ (Translation look-aside buffer) for speeding up address translation. The proposed $$TLB$$ will be capable of storing page table entries for $$16$$ recently referenced virtual pages, in a fast cache that will use the direct mapping scheme. What is the number of tag bits that will need to be associated with each cache entry

(c)$$\,\,\,\,\,$$ Assume that each page table entry contains (besides other information) $$1$$ valid bit, $$3$$ bits for page protection and $$1$$ dirty bit. How many bits are available in page table entry for storing the aging information for the page? Assume that the page size is $$512$$ bytes.

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