1
GATE CSE 1999
MCQ (More than One Correct Answer)
+2
-0.6
A multi-user, multi-processing operating system cannot be implemented on hardware that does not support:
A
Address translation
B
DMA for disk transfer
C
At least two modes of CPU execution (privileged and non-privileged)
D
Demand paging
2
GATE CSE 1999
MCQ (Single Correct Answer)
+2
-0.6
Which of the following actions is/are typically not performed by the operating system when switching context from process $$A$$ to process $$B$$ ?
A
Saving current register values and restoring saved register values for process
B
Changing address translation tables.
C
Swapping out the memory image of process A to the disk.
D
Invalidating the translation look-aside buffer.
3
GATE CSE 1999
MCQ (More than One Correct Answer)
+2
-0.6
Which of the following is/are advantage of virtual memory?
A
Faster access to memory on an average.
B
Processes can be given protected address spaces.
C
Linker can assign addresses independent of where the program will be loaded in physical memory.
D
Programs larger than the physical memory size can be run.
4
GATE CSE 1999
Subjective
+5
-0
A certain computer system has the segmented paging architecture for virtual memory. The memory is byte addressable. Both virtual and physical address spaces contain $${2^{16}}$$ bytes each. The virtual address space is divided into $$8$$ non-overlapping equal size segments. The memory management unit $$(MMU)$$ has a hardware segment table, each entry of which contains the physical address of the page table for the segment. Page table are stored in the main memory and consists of $$2$$ byte page table entries.

(a)$$\,\,\,\,\,$$ What is the minimum page size in bytes so that the page table for a segment requires at most one page to store it? Assume that the page size can only be a power of $$2.$$

(b)$$\,\,\,\,\,$$ Now suppose that the pages size is $$512$$ bytes. It is proposed to provide a $$TLB$$ (Translation look-aside buffer) for speeding up address translation. The proposed $$TLB$$ will be capable of storing page table entries for $$16$$ recently referenced virtual pages, in a fast cache that will use the direct mapping scheme. What is the number of tag bits that will need to be associated with each cache entry

(c)$$\,\,\,\,\,$$ Assume that each page table entry contains (besides other information) $$1$$ valid bit, $$3$$ bits for page protection and $$1$$ dirty bit. How many bits are available in page table entry for storing the aging information for the page? Assume that the page size is $$512$$ bytes.

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